Question

This exercise explores energy efficiency and its relationship with performance. Problems in this exercise assume the following energy consumption for activity in Instruction memory, Registers, and Data memory. You can assume that the other components of the datapath spend a negligible amount of energy.

Assume that components in the datapath have the following latencies. You can assume that the other components of the datapath have negligible latencies.

4.19.1 [10] How much energy is spent to execute an ADD instruction in a single-cycle and in 5-stage pipelined design?

4.19.2 [10] What is the worst-case MIPS instruction in terms of energy consumption, and what is the energy spent to execute it?

4.19.3 [10] If energy reduction is paramount, how would you change the pipelined design? What is the percentage reduction in the energy spent by an LW instruction after this change?

4.19.4 [10] What is the performance impact of your changes from 4.19.3?

4.19.5 [10]We can eliminate the MemRead control signal and have

the data memory be read in every cycle, i.e., we can permanently have MemRead=1. Explain why the processor still functions correctly aft er this change. What is the effect of this change on clock frequency and energy consumption?

4.19.6 [10] If an idle unit spends 10% of the power it would spend

if it were active, what is the energy spent by the instruction memory in each cycle? What percentage of the overall energy spent by the instruction memory does this idle energy represent?

Short answer

4.19.1 – Energy spent is 340 pJ.

4.19.2 – Load instruction is the worst case and energy spent is 480 pJ.

4.19.3 – Percentage reduction is 14.58%

4.19.4 – No Significant performance change take place.

4.19.5 – The clock frequency and energy consumption remain the same,

4.19.6 – The total energy spent is 143.5pJ and the perctange is 2.44%

Step-by-step solution

Step 1:Energy efficiency and performance.

The processors generally have 5 operations and they are I-Mem, Register Read, Register Write, D-Mem Read and D-Mem Write.

The total energy spent for an instruction can be calculated by adding all the energy spent by the operations performed during the operation.

The power used by the instruction unit can be calculated with the formula

$$\begin{gathered} Power=\left(clockcycletime-IMemlatency\right)\times \frac{activeenergyforI-Mem}{LatencyforI-Mem} \\ \times percentageofactivepower \end{gathered}$$

Energy Spent by Instruction memory$=\frac{idleenergy}{totalenergy}$

(4.19.1)Step 2: Finding required energy.

In a single cycle design, ADD instruction has to perform:

• One I-Mem to fetch the instruction.
• Two register read to read the two operands.
• One register write to perform the save operation.

Now the energy required is the total energy required to perform the three operations.

I-Mem = 140, Read = 70 and Write = 60.

Adding all the energies required:

$$\begin{gathered} =140+\left(2\times 70\right)+60 \\ =340 \end{gathered}$$

The required energy is 340 pJ.

(4.19.2)Step 3: Energy consumption for MIPS instruction.

The worst case MIPS instruction is a load instruction because the sum of the energy consumed by memory read and the energy consumed by register write is more than just the energy consumed by memory write.

A load instruction requires, One Instruction memory is read, two registers are read, 1 register is written and 1 memory is read.

Instruction memory = 140 pJ

Read register = 70 pJ

Write register = 60 pJ

Read memory = 140 pJ

The total energy consumed is:

$$\begin{gathered} =140+\left(2\times 70\times \right)+60+140 \\ =480 \end{gathered}$$

The energy spent is 480 pJ

(4.19.3)Step 4: Percentage reduction in energy spent.

A load instruction requires, One Instruction memory is read, two registers are read, 1 register is written and 1 memory is read.

Instruction memory = 140 pJ

Read register = 70 pJ

Write register = 60 pJ

Read memory = 140 pJ

The total energy consumed is:

$$\begin{gathered} =140+\left(2\times 70\right)+60+140 \\ =480 \end{gathered}$$

The energy spent is 480 pJ

If the changes are implemented, the load requires only one register read. This register read is the one required to generate the address. Here, calculate the energy required by a load instruction when these register read signals are used: One Instruction memory is read, one registers is read, 1 register is written and 1 memory is read.

So, the total energy consumed is:

$$\begin{gathered} =140+70+60+140 \\ =410 \end{gathered}$$

The energy spent after changes is 410 pJ.

The energy saved by using register read control is

$$\begin{gathered} =480-410 \\ =70pJ \end{gathered}$$

Percentage reduction

$$\begin{gathered} =\frac{70}{480} \\ =0.145833 \\ \cong 14.58\% \end{gathered}$$

The percentage reduction in energy consumed is 14.58%.

(4.19.4)Step 5: Performance impact.

Consider the following latencies for various components of datapath;

Instruction Memory (I-Mem)=200ps

Control=150ps

Register read or Write=90ps

ALU=90ps

Data Memory (D-Mem) Read or Write=250ps

To calculate the impact on performance due to addition of register read control signals:

Firstly, consider the clock cycle time before the register read control signals are added. In this case, the registers are being read while control unit decodes the instruction.Here, is the longest of the latencies is for I-Mem, which is critical path latency for MEM stage.In the MEM stage, the critical path is the D-Mem latency. Here, value of clock cycle time is 250ps.

Now, consider the clock cycle time after the register read control signals are added.

In this case, the latencies of registers read and control unit are not overlapped. As a result, the latency of ID stage increases by adding the latencies of the two. Here, the new latency of ID stage is given by:

=latency of control unit + latency of register read

=150+90=240ps

Even with the increased latency value of ID stage, it is still less than that for MEM stage (240<250).In the MEM stage, the critical path is the D-Mem latency. Here, value of clock cycle time is 250ps.Finally, it is concluded that there is no change in clock cycle time even after the register read control signals are added to the pipeline.

Hence, with given latencies, there is no impact on the performance of a 5-stage pipeline by addition of register read control signals.

(4.19.5)Step 6: Effect on Clock frequency and Energy consumption.

Consider the case when the MemRead control signal is eliminated and the data memory is read in every cycle. This means that MemRead is always 1. Here, If memory is read in every cycle,

It is either used say for a load instruction.If it not required, (say for non-load instructions that write to a register); it does not get beyond the WB Multiplexor. So, it’s wasted.Or it does not get written to any register at all (Say for all other instructions including stalls). So, it’s wasted here also. So, the processor will still function properly.

Before the change, the memory is read only in cycles when an instruction is in MEM stage. Even with the change memory is read in every cycle. As the clock cycle time allows enough time for memory to be read in each case. So, the change above change does not affect the clock cycle time.

Before the change, the memory is read only in cycles when an instruction is in MEM stage. Even with the change memory read occurs in every cycle. As a result, the same amount of energy is used for data memory read in each case. So, this change also does not affect energy consumption.

Hence, it can be concluded that, even after allowing data memory access in every cycle in lieu of elimination of MemRead Control Signal; the processor function properly and clock frequency and energy consumption remain the same.

(4.19.6)Step 7: Effect on Clock frequency and Energy consumption.

Consider the following latencies for various components of datapath;

Instruction Memory (I-Mem)=200ps

Control=150ps

Register read or Write=90ps

ALU=90ps

Data Memory (D-Mem) Read or Write=250ps

Also consider the energy consumption by various components of datapath as;

Instruction Memory (I-Mem)= 140 pJ

Register read= 70pJ

Register Write=60pJ

Data memory (D-Mem) Read=140pJ

Data memory (D-Mem) write=120pJ

Here, given that the power spent by active instruction memory=140 pJ. Also given the latency of instruction memory= 200ps

Firstly, calculate the clock cycle time; Here, the longest of the latencies is for I-Mem, which is critical path latency for MEM stage. In the MEM stage, the critical path is the D-Mem latency. Here, value of clock cycle time is 250ps.

Now, when unit is idle it spends only 10% of active power.

The power used by instruction memory when unit is idle is given by:

$$\begin{gathered} Power=\left(clockcycletime-IMemlatency\right)\times \frac{activeenergyforI-Mem}{latencyforI-Mem} \\ \times percentageofactivepower \end{gathered}$$

$$\begin{gathered} =\left(250-200\right)\times \frac{140}{200}\times 0.1 \\ =3.5 \end{gathered}$$

Now, calculate the total energy spent on instruction memory (I-Mem)

Total energy spent on instruction memory is given by:

=energy when I-Mem is active + energy when I-Mem is idle

$$\begin{gathered} =140+3.4 \\ =143.5pJ \end{gathered}$$

Finally, calculate the percentage representation of idle energy amongst the total energy.

Energy spent by the instruction memory is given by:

$$\begin{gathered} =\frac{idleenergy}{totalenergy} \\ =\frac{3.5}{143.5} \\ =0.02439 \\ =2.44\% \end{gathered}$$

Hence, the total energy spent on instruction memory (I-Mem) in each cycle is 143.5pJ and the percentage representation of idle energy amongst the total energy spent by the instruction memory is 2.44%