Question

This exercise explores how exception handling affects pipeline design. The first three problems in this exercise refer to the following two instructions:

Instruction 1	Instruction 2
BNE R1,R2, Label	LW R1,0(R1)

4.17.1 Which exceptions can each of these instructions trigger? For each of these exceptions, specify the pipeline stage in which it is detected.

4.17.2 If there is a separate handler address for each exception, show how the pipeline organization must be changed to be able to handle this exception. You can assume that the addresses of these handlers are known when the processor is designed.

4.17.3 If the second instruction is fetched right after the first instruction, describe what happens in the pipeline when the first instruction causes the first exception you listed in 4.17.1. Show the pipeline execution diagram from the time the first instruction is fetched until the time the first instruction of the exception handler is completed.

4.17.4 In vectored exception handling, the table of exception handler

addresses is in data memory at a known (fixed) address. Change the pipeline to implement this exception handling mechanism. Repeat 4.17.3 using this modified pipeline and vectored exception handling.

4.17.5 We want to emulate vectored exception handling (described in 4.17.4) on a machine that has only one fixed handler address. Write the code that should be at that fixed address. Hint: this code should identify the exception, get the right address from the exception vector table, and transfer execution to that handler.

Short answer

4.17.1

Instructions	Exception
BNE R1,R2,Label	Invalid Target Address(EX)
LW R1, 0(R1)	Invalid Data Address(MEM)

4.17.2

The Multiplexor will select the next program counter where the inputs have to be added. Each input will have a constant address of an exception handler. For the appropriate pipeline stage, exception detectors must be added and the output of the detectors must be used to control the pre-PC Mux, and also to convert the NOP instructions.

4.17.3

Instructions
BNE R1,R2, Label	IF	ID	MEM	EXE	WB
Exception		NOP	NOP	NOP	NOP	NOP
Exception			NOP	NOP	NOP	NOP	NOP
LW R1, 0(R1)				IF	ID	MEM	EXE	WB

4.17.4

The address of the handler must be fetched in this method. The code of exception must be added to the address of the exception vector table and the handler’s address for the memory is read to jump to that address. Handle this as a special instruction that compute address in EX, loads the handlers’ address and sets PC in WB.

Instructions
BNE R1,R2, Label	IF	ID	MEM	EXE	WB
Exception		NOP	NOP	NOP	NOP	NOP
vectored exception			IF	ID	MEM	EXE	WB
LW R1, 0(R1)				IF	ID	MEM	EXE	WB

4.17.5

A special instruction is required to change the value from the cause register to the general-purpose register. General-purpose register is saved first, then the cause register gets loaded and the address of the vector table will be added to it. Use the result and jump to the handler.

Step-by-step solution

Determine Exception in pipeline.

Exception occurs when the there occurs error in the instruction execution. When the invalid address is specified there occurs the exception. When the exception occurs in the first instruction, the further instructions in the pipeline will become NOP. After the exception is handled then the instructions in the pipeline gets executed.

Determine the exceptions occurred in the given instructions.

4.17.1

Instructions	Exception
BNE R1,R2,Label	Invalid Target Address(EX)
LW R1, 0(R1)	Invalid Data Address(MEM)

In the instrcution 1, it will jump to the label if the register values are not equal. Here the Label target is not specified, so the invalid target address exception will occur.

In the instruction 2, the load word has noe data address specified, so the exception occurs.

Determine the changes in the pipeline.

4.17.2

The Multiplexor will select the next program counter where the inputs have to be added. Each input will have a constant address of an exception handler. For the appropriate pipeline stage, exception detectors must be added and the output of the detectors must be used to control the pre-PC Mux, and also to convert the NOP instructions.

Determine the pipeline stages.

4.17.3

Until the exception occurs, instructions will be fetced normally. At the time of exception detection, all instructions in the pipleline next to the first will be ocnverted as NOPs. Because of this the second instruction will not be completed and this will never affect the state of the pipeline. In a cycle in which the exception is dectectedm the processor will fetch the first instruction of the exception handler.

Instructions
BNE R1,R2, Label	IF	ID	MEM	EXE	WB
Exception		NOP	NOP	NOP	NOP	NOP
Exception			NOP	NOP	NOP	NOP	NOP
LW R1, 0(R1)				IF	ID	MEM	EXE	WB

Determine the vectored exception handling mechanism.

4.17.4

The address of the handler must be fetched in this method. The code of exception must be added to the address of the exception vector table and the handler’s address for the memory is read to jump to that address. Handle this as a special instruction that compute address in EX, loads the handlers’ address and sets PC in WB.

Instructions
BNE R1,R2, Label	IF	ID	MEM	EXE	WB
Exception		NOP	NOP	NOP	NOP	NOP
vectored exception			IF	ID	MEM	EXE	WB
LW R1, 0(R1)				IF	ID	MEM	EXE	WB

Determine the exception handling mechanism code.

4.17.5

A special instruction is required to change the value from the cause register to the general-purpose register. General-purpose register is saved first, then the cause register gets loaded and the address of the vector table will be added to it. Use the result and jump to the handler.