Question

In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:

IF	ID	EX	MEM	WB
250ps	350ps	150ps	300ps	200ps

Also, assume that instructions executed by the processor are broken down as follows:

alu	beq	lw	sw
45%	20%	20%	15%

4.8.1 [5] What is the clock cycle time in a pipelined and non-pipelined processor?

4.8.2 [10] What is the total latency of an LW instruction in a pipelined and non-pipelined processor?

4.8.3 [10] If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? 4.8.4 [10] Assuming there are no stalls or hazards, what is the utilization of the data memory?

4.8.5 [10] Assuming there are no stalls or hazards, what is the utilization of the write-register port of the “Registers” unit? 4.8.6 [30] Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction finishes before another is fetched. In this organization, an instruction only goes through stages it actually needs (e.g., ST only takes 4 cycles because it does not need the WB stage). Compare clock cycle times and execution times with singlecycle, multi-cycle, and pipelined organization.

Short answer

4.8.1

350 ps is the required clock cycle timein a pipelined processor.

1250 psis the required clock cycle timein a non-pipelined processor.

4.8.2

The total latency isin a pipelined processor is 1750ps.

The total latency isin a non-pipelined processor is 1250ps.

4.8.3

The new clock cycle time is 300ps.

4.8.4

There will be 35% utilization of the data memory for the given condition.

4.8.5

There will be 65% utilization of the port “write-register”for the given condition.

4.8.6

The multi-cycle execution time is 4.20.

And the single-cycle execution time is 3.57.

Step-by-step solution

Define the concept.

4.8.1

For thepipelined processor,

The latency of each cycle is referred tothe clock cycle time.

The clock cycle timein a pipelined processor can’t becomputed by the sum of all latency of the stages.

For the non-pipelined processor,

The clock cycle timein a non-pipelined processor iscomputed by the sum of all latency of the stages.

4.8.2

Given that,

Individual stages of the data-path	Latency
IF	250ps
ID	350ps
EX	150ps
MEM	300ps
WB	200ps

Given that ,

Instruction	Break down
lw	20%

For thepipelined processor,

The latency of each cycle is 350 ps.

So, the latency of 5 cycles is ps (350x5) ps =1750 ps

The total latency ofthe “LW” instructionisin a pipelined processor is 1750ps.

For the non-pipelined processor,

Hence, (250+350+150+300+200) ps =1250 ps.

The total latencyof the “LW” instructionin a non-pipelined processor is 1250ps.

4.8.3

Let’s consider, the stage of the specified pipelined data path becomes split into two new stages and each of the new split stages has the half latency of the initial stage.

According to the given condition, the new clock cycle time is 300ps.

4.8.4

The instruction “lw” or load word has the break down 20%.

The instruction “sw” or store word has the break down 15%.

Hence, (20+15) %=35%.

The utilization of the data memory is referred to the sum of the break-down of the instruction “lw” and “sw”.

4.8.5

The instruction “ALU” or load word has the break down 45%.

The instruction “Beq” or store word has the break down 120%.

Hence, (20+45)%=65%.

The utilizationthe port “write-register”for the specified condition is referred to the sum of the break-down of the instruction “ALU” and “Beq”.

4.8.6

Let’s consider, four cycles are taken by “ST” as any WB stages are not required for this.

For the multi-cycle,

$$\begin{gathered} \left(\right(0.20\times 5)+(0.80\times 4\left)\right) \\ =1.00+3.20 \\ =4.20 \end{gathered}$$

The multi-cycle execution time is 4.20.

For the single-cycle,

$$\begin{gathered} \frac{1250ps}{350ps} \\ =3.57 \end{gathered}$$

And the single-cycle execution time is 3.57.

 Determine the calculation.

4.8.1

Given that,

Individual stages of the data-path	Latency
IF	250ps
ID	350ps
EX	150ps
MEM	300ps
WB	200ps

For thepipelined processor,

The latency of each cycle is 350 ps.

350 ps is the required clock cycle time in a pipelined processor.

For the non-pipelined processor,

Hence, (250+350+150+300+200) ps =1250 ps.

1250 psis the required clock cycle timein a non-pipelined processor.

4.8.2

Given that,

Individual stages of the data-path	Latency
IF	250ps
ID	350ps
EX	150ps
MEM	300ps
WB	200ps

For thepipelined processor,

The latency of each cycle is 350 ps.

So, the latency of 5 cycle is ps $\left(350\times 5\right)$ps=1750 ps

The total latency isin a pipelined processor is 1750ps.

For the non-pipelined processor,

Hence, (250+350+150+300+200) ps=1250 ps.

The total latency isin a non-pipelined processor is 1250ps.

4.8.3

Let’s consider, one stage of the pipelined data path is split into two new

Stage and each of the new split stages has the half latency of the initial stage.

According to the given condition, the new clock cycle time is 300ps.

4.8.4

Given that,

Instruction	Break down
Alu	45%
Beq	20%
lw	20%
sw	15%

The instruction “lw” or load word has the break down 20%.

The instruction “sw” or store word has the break down 15%.

Hence, (20+15)%=35%.

There will be 35% utilization of the data memory for the given condition.

4.8.5

Given that,

Instruction	Break down
Alu	45%
Beq	20%
lw	20%
sw	15%

The instruction “ALU” or load word has the break down 45%.

The instruction “Beq” or store word has the break down 120%.

Hence, (20+45)%=65%.

There will be 65% utilization of the port “write-register”for the given condition.

4.8.6

Let’s consider, four cycles are taken by “ST” as any WB stages are not required for this.

For the multi-cycle,

The multi-cycle execution time is 4.20.

For the single-cycle,

And the single-cycle execution time is 3.57.