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Chapter 4: 7. (page 360)

In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: 10101100011000100000000000010100. Assume that data memory is all zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched:

r0

r1

r2

r3

r4

r5

r6

r8

r12

r31

0

–1

2

–3

–4

10

6

8

2

–16

4.7.1 [5] What are the outputs of the sign-extend and the jump “Shift left 2” unit (near the top of Figure 4.24) for this instruction word?

4.7.2 [10] What are the values of the ALU control unit’s inputs for this instruction?

4.7.3 [10] What is the new PC address after this instruction is executed? Highlight the path through which this value is determined.

4.7.4 [10] For each Mux, show the values of its data output during the execution of this instruction and these register values.

4.7.5 [10] For the ALU and the two add units, what are their data input values?

4.7.6 [10] What are the values of all inputs for the “Registers” unit?

Short Answer

Expert verified

4.7.1

The outputs of the sign-extend is 00000000000000000000000000010100

The outputs of the jump “Shift left 2” unit is 0001100010000000000001010000

4.7.2

The values of the ALU control unit’s inputs –00 [ALUOp],010100 [Instruction]

4.7.3

The required values:

The new PC address - PC + 4.

The required path will bePC to Add (PC + 4) to branch Mux to jump Mux to PC.

4.7.4

The required values:

WrReg Mux-2 or 0 (RegDst is X)

ALU Mux-20

Mem/ALU Mux-X

Branch Mux-PC + 4

Jump Mux-PC + 4

4.7.5

The required values:

ALU: −3 and 20

Add (PC + 4):PC and 4

Add (Branch) : PC+4 and 20x4

4.7.6

The required values:

Read Register 1: 3

Read Register 2:2

Write Register:X

Write Data:X

RegWrite : 0

Step by step solution

01

Define the concept.

4.7.1

Given instruction word is 10101100011000100000000000010100.

Also given that the data memory is all zeros and that the processor’s registers have the values:

r0

0

r1

-1

r2

2

r3

-3

r4

-4

r5

10

r6

6

r8

8

r12

2

r31

-16

4.7.2

Given instruction word is 10101100011000100000000000010100.

Also given that the data memory is all zeros and that the processor’s registers have the values: 00for the 2 bit ALUOp and010100 for the 6 bit Instruction

4.7.3

After execution of the specified instruction, the new PC address will be PC + 4.

Thee value is computed by the path of “ PC to Add (PC + 4) to branch Mux to jump Mux to PC”.

4.7.4

During the execution of the specified instruction, the values of its data output and these corresponding values of registers are different.

4.7.5

The data input values for the ALU and the two “add” units are computed as,

For the ALU: −3 and 20, for the Add (PC + 4) : PC and 4, for the Add (Branch) : PC+4 and 20x4

4.7.6

The components of the “register” unit are the WrReg Mux, the ALU Mux the Mem/ALU Mux, the Branch Mux the Jump Mux. And their values are 3, 2, X, X, 0 respectively.

02

Determine the calculation. 

4.7.1

Given instruction word is 10101100011000100000000000010100.

Also given that the data memory is all zeros and that the processor’s registers have the values:

r0

0

r1

-1

r2

2

r3

-3

r4

-4

r5

10

r6

6

r8

8

r12

2

r31

-16

Following tabulated values represent the outputs of the sign-extend and the jump “Shift left 2” unit for the given instruction word.

The outputs of the sign extend

The jump “Shift left 2” unit

00000000000000000000000000010100

0001100010000000000001010000

4.7.2

Given instruction word is 10101100011000100000000000010100.

Also given that the data memory is all zeros and that the processor’s registers have the values:

r0

0

r1

-1

r2

2

r3

-3

r4

-4

r5

10

r6

6

r8

8

r12

2

r31

-16

The required values:

ALUOp

00

Instruction

010100

4.7.3

After execution of the instruction, the new PC address will be PC + 4.

The Highlighted path by which the value is computed - PC to Add (PC + 4) to branch Mux to jump Mux to PC.

4.7.4

During the execution of the specified instruction, the values of its data output and these corresponding values of registers are written below for every Mux.

WrReg Mux

2 or 0 (RegDst is X)

ALU Mux

20

Mem/ALU Mux

X

Branch Mux

PC + 4

Jump Mux

PC + 4

4.7.5

The data input values for the ALU and the two “add” units are written below:

ALU

−3 and 20

Add (PC + 4)

PC and 4

Add (Branch)

PC+4 and 20x4

4.7.6

The following values have represented all inputs for the “Registers” unit:

Read Register 1

3

Read Register 2

2

Write Register

X

Write Data

X

RegWrite

0

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Most popular questions from this chapter

Question: Problems in this exercise assume that logic blocks needed to implement a processor’s datapath have the following latencies: I-Mem Add Mux ALU Regs D-Mem Sign-Extend Shift-Left-2 200ps 70ps 20ps 90ps 90ps 250ps 15ps 10ps 4.4.1 [10] If the only thing we need to do in a processor is fetch consecutive instructions (Figure 4.6), what would the cycle time be? 4.4.2 [10] Consider a datapath similar to the one in Figure 4.11, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would the cycle time be for this datapath? 4.4.3 [10] Repeat 4.4.2, but this time we need to support only conditional PC-relative branches. The remaining three problems in this exercise refer to the datapath element Shift - left -2: 4.4.4 [10] Which kinds of instructions require this resource? 4.4.5 [20] For which kinds of instructions (if any) is this resource on the critical path? 4.4.6 [10] Assuming that we only support beq and add instructions, discuss how changes in the given latency of this resource affect the cycle time of the processor. Assume that the latencies of other resources do not change.

This exercise explores energy efficiency and its relationship with performance. Problems in this exercise assume the following energy consumption for activity in Instruction memory, Registers, and Data memory. You can assume that the other components of the datapath spend a negligible amount of energy.

Assume that components in the datapath have the following latencies. You can assume that the other components of the datapath have negligible latencies.

4.19.1 [10] How much energy is spent to execute an ADD instruction in a single-cycle and in 5-stage pipelined design?

4.19.2 [10] What is the worst-case MIPS instruction in terms of energy consumption, and what is the energy spent to execute it?

4.19.3 [10] If energy reduction is paramount, how would you change the pipelined design? What is the percentage reduction in the energy spent by an LW instruction after this change?

4.19.4 [10] What is the performance impact of your changes from 4.19.3?

4.19.5 [10]We can eliminate the MemRead control signal and have

the data memory be read in every cycle, i.e., we can permanently have MemRead=1. Explain why the processor still functions correctly aft er this change. What is the effect of this change on clock frequency and energy consumption?

4.19.6 [10] If an idle unit spends 10% of the power it would spend

if it were active, what is the energy spent by the instruction memory in each cycle? What percentage of the overall energy spent by the instruction memory does this idle energy represent?

The importance of having a good branch predictor depends on how often conditional branches are executed. Together with branch predictor accuracy, this will determine how much time is spent stalling due to mispredicted branches. In this exercise, assume that the breakdown of dynamic instructions into various instruction categories is as follows:

R-Type

BEQ

JMP

LW

SW

40%

25%

5%

25%

5%

Also, assume the following branch predictor accuracies:

Always-Taken

Always-Not-Taken

2-Bit

45%

55%

85%

4.15.1 [10] Stall cycles due to mispredicted branches increase the CPI. What is the extra CPI due to mispredicted branches with the always-taken predictor? Assume that branch outcomes are determined in the EX stage, that there are no data hazards, and that no delay slots are used.

4.15.2 [10] Repeat 4.15.1 for the “always-not-taken” predictor.

4.15.3 [10] Repeat 4.15.1 for for the 2-bit predictor.

4.15.4 [10] With the 2-bit predictor, what speedup would be achieved if we could convert half of the branch instructions in a way that replaces a branch instruction with an ALU instruction? Assume that correctly and incorrectly predicted instructions have the same chance of being replaced. 4.17 Exercises 367 4.15.5 [10] With the 2-bit predictor, what speedup would be achieved if we could convert half of the branch instructions in a way that replaced each branch instruction with two ALU instructions? Assume that correctly and incorrectly predicted instructions have the same chance of being replaced.

4.15.6 [10] Some branch instructions are much more predictable than others. If we know that 80% of all executed branch instructions are easy-to-predict loop-back branches that are always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining 20% of the branch instructions?

Question: Consider the following instruction: Instruction: AND Rd,Rs,Rt Interpretation: Reg[Rd] = Reg[Rs] AND Reg[Rt] 4.1.1 [5] What are the values of control signals generated by the control in Figure 4.2 for the above instruction? 4.1.2 [5] Which resources (blocks) perform a useful function for this instruction? 4.1.3 [10] Which resources (blocks) produce outputs, but their outputs are not used for this instruction? Which resources produce no outputs for this instruction?.

Question: In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: 10101100011000100000000000010100. Assume that data memory is all zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched:

r0

r1

r2

r3

r4

r5

r6

r8

r12

r31

0

–1

2

–3

–4

10

6

8

2

–16

4.7.1 [5] What are the outputs of the sign-extend and the jump “Shift left 2” unit (near the top of Figure 4.24) for this instruction word?

4.7.2 [10] What are the values of the ALU control unit’s inputs for this instruction?

4.7.3 [10] What is the new PC address after this instruction is executed? Highlight the path through which this value is determined.

4.7.4 [10] For each Mux, show the values of its data output during the execution of this instruction and these register values.

4.7.5 [10] For the ALU and the two add units, what are their data input values?

4.7.6 [10] What are the values of all inputs for the “Registers” unit?
See all solutions

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