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Chapter 4: 4. (page 358)

Problems in this exercise assume that logic blocks needed to implement a processor’s datapath have the following latencies: I-Mem Add Mux ALU Regs D-Mem Sign-Extend Shift-Left-2 200ps 70ps 20ps 90ps 90ps 250ps 15ps 10ps 4.4.1 [10] If the only thing we need to do in a processor is fetch consecutive instructions (Figure 4.6), what would the cycle time be? 4.4.2 [10] Consider a datapath similar to the one in Figure 4.11, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would the cycle time be for this datapath? 4.4.3 [10] Repeat 4.4.2, but this time we need to support only conditional PC-relative branches. The remaining three problems in this exercise refer to the datapath element Shift - left -2: 4.4.4 [10] Which kinds of instructions require this resource? 4.4.5 [20] For which kinds of instructions (if any) is this resource on the critical path? 4.4.6 [10] Assuming that we only support beq and add instructions, discuss how changes in the given latency of this resource affect the cycle time of the processor. Assume that the latencies of other resources do not change.

Short Answer

Expert verified

4.4.1

The required clock cycle time will be 200 ps.

4.4.2

The required cycle time will be 315 ps.

4.4.3

The required cycle time will be 420 ps.

4.4.4

PC-relative branches are required for this kind of resources.

4.4.5

Including the critical path, the required cycle time for the mentioned datapath is 315ps.

4.4.6

The cycle time will be 530 ps.

Step by step solution

01

Define the concept.

4.4.1

The unit “I-Mem” takes a higher latency than the “Add” unit according to the given data.

Hence, the clock cycle time is the same as the latency of the “IMem”.

4.4.2

Given that the critical path for this specified instruction is following below-

  • The memory of the instruction,
  • The “Sign-extend”
  • The “Shiftleft-2” for getting the offset,
  • The unit “Add” for computing the new PC,
  • And the “Mux” for selecting the value not for selecting the values of PC + 4.

The unit “I-Mem” takes a higher latency than the “Add” unit according to the given data.

4.4.3

Conditional branches have the same high-latency path that can able to compute the branch address, the unconditional branches. Also it has the high-latency path that can able to go through the mux,registers, and the ALU for computing the condition of the PCSrc.

4.4.4

This kind of resource requires the PC-relative branches

4.4.5

The critical path takes the highest time for execution.Including the critical path, the required cycle time for the mentioned datapath is 315ps.

4.4.6

After supporting only “beq” and “add” instruction, the required cycle time of the PC-relative branches = (440+90) ps = 530 ps.

02

Determine the calculation. 

4.4.1

Given that,

Name of the logic block

The latency

I-Mem

200ps

Add

70ps

Also given that the fetch consecutive instructions are performed in a processor as the mentioned figure, then the clock cycle time will be 200 ps. As the clock cycle time is the same as the latency of the “IMem”.

4.4.2

Given that,

Name of the logic block

The latency

I-Mem

200ps

Add

70ps

Mux

20ps

ALU

90ps

Regs

90ps

D-Mem

250ps

Sign-Extend

15ps

Shift-Left-2

10ps

The required cycle time for the mentioned datapath = (200ps + 15ps + 10ps + 70ps + 20ps) = 315ps

4.4.3

Given that,

Name of the logic block

The latency

I-Mem

200ps

Add

70ps

Mux

20ps

ALU

90ps

Regs

90ps

D-Mem

250ps

Sign-Extend

15ps

Shift-Left-2

10ps

The required cycle time for supporting only the branches of conditional PC-relative =( 200ps + 90ps + 20ps + 90ps + 20ps) = 420ps

4.4.4

PC-relative branches are required for this kind of resource.

4.4.5

Including the critical path, the required cycle time for the mentioned datapath = (200ps + 15ps + 10ps + 70ps + 20ps) = 315ps

4.4.6

If the latencies of other resources are not changes then,

After supporting only “beq” and “add” instruction, the required cycle time of the PC-relative branches = (440+90) ps = 530 ps.

This is recognized as a critical path. As this path takes the highest time for execution.

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Most popular questions from this chapter

This exercise explores how exception handling affects pipeline design. The first three problems in this exercise refer to the following two instructions:

Instruction 1

Instruction 2

BNE R1,R2, Label

LW R1,0(R1)

4.17.1 Which exceptions can each of these instructions trigger? For each of these exceptions, specify the pipeline stage in which it is detected.

4.17.2 If there is a separate handler address for each exception, show how the pipeline organization must be changed to be able to handle this exception. You can assume that the addresses of these handlers are known when the processor is designed.

4.17.3 If the second instruction is fetched right after the first instruction, describe what happens in the pipeline when the first instruction causes the first exception you listed in 4.17.1. Show the pipeline execution diagram from the time the first instruction is fetched until the time the first instruction of the exception handler is completed.

4.17.4 In vectored exception handling, the table of exception handler

addresses is in data memory at a known (fixed) address. Change the pipeline to implement this exception handling mechanism. Repeat 4.17.3 using this modified pipeline and vectored exception handling.

4.17.5 We want to emulate vectored exception handling (described in 4.17.4) on a machine that has only one fixed handler address. Write the code that should be at that fixed address. Hint: this code should identify the exception, get the right address from the exception vector table, and transfer execution to that handler.

Consider the following instruction: Instruction: AND Rd,Rs,Rt Interpretation: Reg[Rd] = Reg[Rs] AND Reg[Rt] 4.1.1 [5] What are the values of control signals generated by the control in Figure 4.2 for the above instruction? 4.1.2 [5] Which resources (blocks) perform a useful function for this instruction? 4.1.3 [10] Which resources (blocks) produce outputs, but their outputs are not used for this instruction? Which resources produce no outputs for this instruction?

Question: Problems in this exercise assume that logic blocks needed to implement a processor’s datapath have the following latencies: I-Mem Add Mux ALU Regs D-Mem Sign-Extend Shift-Left-2 200ps 70ps 20ps 90ps 90ps 250ps 15ps 10ps 4.4.1 [10] If the only thing we need to do in a processor is fetch consecutive instructions (Figure 4.6), what would the cycle time be? 4.4.2 [10] Consider a datapath similar to the one in Figure 4.11, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would the cycle time be for this datapath? 4.4.3 [10] Repeat 4.4.2, but this time we need to support only conditional PC-relative branches. The remaining three problems in this exercise refer to the datapath element Shift - left -2: 4.4.4 [10] Which kinds of instructions require this resource? 4.4.5 [20] For which kinds of instructions (if any) is this resource on the critical path? 4.4.6 [10] Assuming that we only support beq and add instructions, discuss how changes in the given latency of this resource affect the cycle time of the processor. Assume that the latencies of other resources do not change.

Consider the following loop.

loop:lw r1,0(r1)

and r1,r1,r2

lw r1,0(r1)

lw r1,0(r1)

beq r1,r0,loop

Assume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots, and that the pipeline has full forwarding support. Also, assume that many iterations of this loop are executed before the loop exits.

4.11.1 Show a pipeline execution diagram for the third iteration of this loop, from the cycle in which we fetch the first instruction of that iteration up to(but not including) the cycle in which we can fetch the first instruction of the next iteration. Show all instructions that are in the pipeline during these cycles (not just those from the third iteration).

4.11.2 How often (as a percentage of all cycles) do we have a cycle in which all five pipeline stages are doing useful work?

Question: The basic single-cycle MIPS implementation in Figure 4.2 can only implement some instructions. New instructions can be added to an existing Instruction Set Architecture (ISA), but the decision whether or not to do that depends, among other things, on the cost and complexity the proposed addition introduces into the processor datapath and control. The first three problems in this exercise refer to the new instruction: Instruction: LWI Rt,Rd(Rs) Interpretation: Reg[Rt] = Mem[Reg[Rd]+Reg[Rs]] 4.2.1 [10] Which existing blocks (if any) can be used for this instruction? 4.2.2 [10] which new functional blocks (if any) do we need for this instruction? 4.2.3 [10] what new signals do we need (if any) from the control unit to support this instruction?
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