Question

When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off . In the following three problems, assume that we are starting with a datapath from Figure 4.3, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 ps, and 100 ps, respectively, and costs of 1000, 30, 10, 100, 200, 2000, and 500, respectively. Consider the addition of a multiplier to the ALU. This addition will add 300 ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction. 4.3.1 [10] What is the clock cycle time with and without this improvement? 4.3.2 [10] What is the speedup achieved by adding this improvement? 4.3.3 [10] Compare the cost/performance ratio with and without this improvement.

Short answer

4.3.1

The clock cycle time with and without this improvement is 1130 and 1430 respectively.

4.3.2

No speedup is achieved.

4.3.3

The cost/performance ratio with and without this improvement is.

Step-by-step solution

Define the concept.

4.3.1

$Clockcycletime=(I-Mem+Reg+Mux+ALU+D-Mem+Mux)$

4.3.2

Running time = number of instruction x latency

4.3.3

$Clockcycletime=(I-mem+(2\times add)+(3\times mux)+ALU+reg+D-mem+controlblocks)$

Determine the calculation.

4.3.1

Given that, the I-Mem, Add, Mux, ALU, Regs, D-Mem, and thecontrol blocks have latencies of 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 psand costs of the mentioned latencies are respectively 1000, 30, 10, 100, 200, 2000, and 500.

It is considered that the addition of a multiplier to the ALU. Also, 300 ps to the latency of the ALU will be added to this addition and will add a cost of 600 to the ALU. The result will be 5% fewer instructions as there is no need to emulate the MUL instruction.

So, the clock cycle time without this improvement= (400+30+200+120+350+30) = 1130.

So, the clock cycle time with the improvement is

(400+30+200+120+300+350+30) = 1430[As, 300 is the additional latency of ALU which is added for improvement].

4.3.2

Let’s assume, the 1130 ps is the latency of the 1000 instructions.

Hence the running time will be 1130000.

The 1430 ps is the latency of the 950 instructions.

Hence the running time will be 1358500.

Hence, 1358500 – 1130000 = 2,28,500.

No speedup is achieved by adding the specified instruction (MUL) rather than

running time will be decreased by 2,28,500.

4.3.3

Let’s assume the increasing cost to 10000000.

The comparison of the cost and the performance:

Clock cycle time = (1000+(2x30)+(3x10)+100+200+2000+500)

= 3890

$$\begin{gathered} Costperformanceratio=\frac{\cos t}{{\displaystyle \frac{1}{clockcycletimewithoutimprovement}}} \\ =\frac{10000000}{{\displaystyle \frac{1}{1130}}} \\ =10000000\times 1130 \\ =0.00113sec \end{gathered}$$

$$\begin{gathered} Costperformance=\left(\frac{3890}{{\displaystyle \frac{1}{0.00113}}}\right) \\ =4.4 \\ Cost=3890+600=4490 \\ 10000000\times 1430\times 0.95=1358000000ps \\ =0.0013585sec \\ \frac{4490}{{\displaystyle \frac{1}{0.0013585}}}=6.1 \\ Cost=3890-400=3490 \\ 10000000\times 1430\times 0.95=13000000ps \\ =0.00113sec \\ \frac{3490}{{\displaystyle \frac{1}{0.00113}}}=3.9437 \end{gathered}$$

Hence, there is no improvement.