Question

The basic single-cycle MIPS implementation in Figure 4.2 can only implement some instructions. New instructions can be added to an existing Instruction Set Architecture (ISA), but the decision whether or not to do that depends, among other things, on the cost and complexity the proposed addition introduces into the processor datapath and control. The first three problems in this exercise refer to the new instruction: Instruction: LWI Rt,Rd(Rs) Interpretation: Reg[Rt] = Mem[Reg[Rd]+Reg[Rs]] 4.2.1 [10] Which existing blocks (if any) can be used for this instruction? 4.2.2 [10] which new functional blocks (if any) do we need for this instruction? 4.2.3 [10] what new signals do we need (if any) from the control unit to support this instruction?

Short answer

4.2.1

The instruction memory, the register read ports, the path which can be able to pass the immediate to ALU, and the RegWrite (register write port) can be used for this specified instruction.

4.2.2

It is needed to extend the existing ALU to do shifts (SLL, to extend the offset to 32bit value).

4.2.3

It is needed to change the operation of the ALU control signals for supporting the operation of the SLL in ALU.

Step-by-step solution

Define the concept.

4.2.1

“lw” One of the R-type MIPS instructions, “lw” is used for loading the word.

“LWI Rt,Rd(Rs)” is the way of declaring the instruction where “LWI” is the name of the instruction and “Rt” is the address of the destination register, and “Rd(Rs)” is the offset of the address of the source register.

4.2.2

“sll $t3 $t4 1”One of the “R-type (Register type)” MIPS instructions where “$t4” is the source register, “$t3” is the destination register, and “1” is the specified shift amount. The purpose of using this is to shift the value of the register to the left by the specified shift amount.

4.2.3

“sll” is used to shift the value of the register to the left by a specified shift amount.

Determine the calculation.

4.2.1

The specified picture is Figure 4.2.

It is also given that the instruction is “LWI Rt,Rd(Rs)” and the interpretation is “Reg[Rt] = Mem[Reg[Rd]+Reg[Rs]].”

The names of the required existing blocks that can be used for this specified instruction are as follows:

• The instruction memory
• The register read ports
• The path that can be able to pass the immediate to ALU.
• And RegWrite (register write port).

4.2.2

The name of the new functional blocks is to extend the existing ALU to do shifts (SLL, to extend the offset to 32bit value).

4.2.3

The name of the required new signals from the control unit to support this instruction is to change the operation of the ALU control signals for supporting the operation of the SLL in ALU.