Question

Consider the following instruction: Instruction: AND Rd,Rs,Rt Interpretation: Reg[Rd] = Reg[Rs] AND Reg[Rt] 4.1.1 [5] What are the values of control signals generated by the control in Figure 4.2 for the above instruction? 4.1.2 [5] Which resources (blocks) perform a useful function for this instruction? 4.1.3 [10] Which resources (blocks) produce outputs, but their outputs are not used for this instruction? Which resources produce no outputs for this instruction?

Short answer

4.1.1

The required values are written below:

RegWrite	Memread	ALUMUX	MemWrite	ALUOP	RegMux	Branch
0	0	1	1	Add	X	0

4.1.2

All resources (blocks) perform a useful function for this instruction except the “branch add” unit and write the port of the registers.

4.1.3

Resources	Output
Branch add	Data memory[Not used output]
Branch add, second the read port register	No outputs

Step-by-step solution

Define the concept.

4.1.1

The control signal “ALUMux” can control Mux.

The output of the register file is selected at the ALU input, 0 (Reg) And the immediate from the instruction word is selected by “1(Imm)” as the second input to ALU.

The control signal “RegMux” can control Mux at the data input to the register file.

The output of the ALU is selected by the “0” ALU and the output of the memory is selected by “0”Mem.

The value “X” is denoted as “don’t care.” So it does not care if the signal is 0 or 1.

4.1.2

The resource (blocks) “branch add” does not perform a useful function for this instruction. It writes the port of the registers.

4.1.3

The “branch add” produces the data memory as an output. This output is not used. However, the resource “branch add, second the read port register” produces no output.

Determine the calculation.

4.1.1

The specified picture is Figure 4.2.

It is also given that the instruction is “AND Rd,Rs,Rt” and the interpretation is “Reg[Rd] = Reg[Rs] AND Reg[Rt].”

For the specified instruction, the control generated the values of control signals in the mentioned figure-4.2.

RegWrite	Memread	ALUMUX	MemWrite	ALUOP	RegMux	Branch
0	0	1	1	Add	X	0

Here “X” is denoted as a “don’t care” situation.

4.1.2

All resources (blocks) perform a useful function for this instruction but the resource (blocks) “branch add” does not perform a useful function for this instruction. It writes the port of the registers.

4.1.3

The “branch add” produces the data memory as an output. This output is not used where the “branch add, second the read port register” produces no output.