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Figure B.8.8 on page B-55 illustrates the implementation of the register file for the MIPS datapath. Pretend that a new register file is to be built, but that there are only two registers and only one read port, and that each register has only 2 bits of data. Redraw Figure B.8.8 so that every wire in your diagram corresponds to only 1 bit of data (unlike the diagram in Figure B.8.8, in which some wires are 5 bits and some wires are 32 bits). Redraw the registers using D flipflops. You do not need to show how to implement a D flip-flop or a multiplexor

Short Answer

Expert verified

The figure B8.8 would be redrawn for 2 -bit register file using D flipflops is as follows:

Step by step solution

01

Step 1:Determine register file

A register file will have two read ports and the one write port. Five inputs will be given to the register file, whereas the outputs will be two. A register file will have the set of registers that can be read and written. The array of registers can be build using the D flip-flops. For reading register there will be no state change occur. For writing, it needs three inputs such as register number, write data and the clock signal.

02

Redraw the fig B.8.8. by using D flip-flops

Given that the new register file has two registers and only one read port. Each registers have only 2 bits of data.

Refer Fig B.8.8 to know the implementation of a register file.

The redrawn diagram using D flip-flops with one bit data.

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Most popular questions from this chapter

A.8 [5] Using SPIM, write and test a program that reads in a positive integer using the SPIM system calls. If the integer is not positive, the program should terminate with the message “Invalid Entry”; otherwise the program should print out the names of the digits of the integers, delimited by exactly one space. For example, if the user entered “728,” the output would be “Seven Two Eight.”

A systolic array is an example of an MISD machine. A systolic array is a pipeline network or “wavefront” of data processing elements. Each of these elements does not need a program counter since execution is triggered by the arrival of data. Clocked systolic arrays compute in “lock-step” with each processor undertaking alternate compute and communication phases.

6.12.1 [10] Consider proposed implementations of a systolic array (you can find these in on the internet or in technical publications). Then attempt to program the loop provided in Exercise 6.11 using this MISD model. Discuss any difficulties you encounter.

6.12.2 [10] Discuss the similarities and differences between an MISD and SIMD machine. Answer this question in terms of data-level parallelism.

Implement a switching network that has two data inputs (Aand B), two data outputs (Cand D), and a control input (S). If Sequals 1, the network is in pass-through mode, and Cshould equal A, and Dshould equal B. If Sequals 0, the network is in crossing mode, and Cshould equal B, and Dshould equal A.

Question: Matrix multiplication plays an important role in a number of applications. Two matrices can only be multiplied if the number of columns of the first matrix is equal to the number of rows in the second. Let’s assume we have an m × n matrix A and we want to multiply it by an n × p matrix B. We can express their product as an m × p matrix denoted by AB (or A ⋅ B). If we assign C = AB, and ci,j denotes the entry in C at position (i, j), then for each element i and j with 1 ≤ i ≤ m and 1 ≤ j ≤ p. Now we want to see if we can parallelize the computation of C. Assume that matrices are laid out in memory sequentially as follows: a1,1, a2,1, a3,1, a4,1, …, etc

6.6.1 [10] Assume that we are going to compute C on both a single-core shared memory machine and a 4-core shared-memory machine. Compute the speedup we would expect to obtain on the 4-core machine, ignoring any memory issues.

6.6.2 [10] Repeat Exercise 6.6.1, assuming that updates to C incur a cache miss due to false sharing when consecutive elements are in a row (i.e., index i) are updated.

6.6.3 [10] How would you fix the false sharing issue that can occur?

Question: Many computer applications involve searching through a set of data and sorting the data. A number of efficient searching and sorting algorithms have been devised in order to reduce the runtime of these tedious tasks. In this problem we will consider how best to parallelize these tasks.

(6.3.1) Consider the following binary search algorithm (a classic divide and conquer algorithm) that searches for a value X in a sorted N-element array A and returns the index of matched entry:

BinarySearch(A[0..N-1], X) {

low=0

high=N-1

while(low<high) {

mid=(low<=high). {

mid = (low+high)/2

if (A[mid]>X)

high = mid -1

else if (A[mid]<X)

low=mid+1

else

return mid //found

}

return -1 //not found

}

Assume that you have Y cores on a multi-core processor to run BinarySearch. Assuming that Y is much smaller than N, express the speedup factor you might expect to obtain for values of Y and N. Plot these on a graph.

(6.3.2) Next, assume that Y is equal to N. How would this affect your conclusions in your previous answer? If you were tasked with obtaining the best speedup factor possible (i.e. strong scaling), explain how you might change this code to obtain it.

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