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Question Title: Q2E

Question:You are trying to bake 3 blueberry pound cakes. Cake ingredients are as follows:

1 cup butter, softened

1 cup sugar

4 large eggs

1 teaspoon vanilla extract

1/2 teaspoon salt

1/4 teaspoon nutmeg

1 1/2 cups flour

1 cup blueberries

The recipe for a single cake is as follows:

Step 1: Preheat oven to 325°F (160°C). Grease and flour your cake pan.

Step 2: In large bowl, beat together with a mixer of butter and sugar at medium speed until light and fluffy. Add eggs, vanilla, salt, and nutmeg. Beat until thoroughly blended. Reduce mixer speed to low and add flour, 1/2 cup at a time, beating just until blended.

Step 3: Gently fold in blueberries. Spread evenly in a prepared baking pan. Bake for 60 minutes.

6.2.1 Your job is to cook 3 cakes as efficiently as possible. Assuming that you only have one oven large enough to hold one cake, one large bowl, one cake pan, and one mixer, come up with a schedule to make three cakes as quickly as possible. Identify the bottlenecks in completing this task.

6.2.2 Assume now that you have three bowls, 3 cake pans, and 3 mixers. How much faster is the process now that you have additional resources?

6.2.3 Assume now that you have two friends that will help you cook, and that you have a large oven that can accommodate all three cakes. How will this change the schedule you arrived at in Exercise 6.2.1 above?

6.2.4 Compare the cake-making task to computing 3 iterations of a loop on a parallel computer. Identify data-level parallelism and task-level parallelism in the cake-making loop.

Short Answer

Expert verified

6.2.1 The schedule for making three cakes as quickly as possible:

  • Preheat the Oven

  • Mix ingredients in a bowl for Cake 1

  • Fill the cake pan with the contents of the bowl and bake Cake 1. Meanwhile, mix the ingredients for Cake 2 in a bowl.

  • After cake 1 is baked, empty the cake pan. Fill the cake pan with the ingredients for cake 2 and bake cake 2. Meanwhile, mix the ingredients for Cake 3 in a bowl.

  • After cake 2 is baked, empty the cake pan. Fill the cake pan with the ingredients for cake 3 and bake cake 3.

  • Finish baking cake 3 and empty the cake pan.

The bottleneck of this task is having one oven with the capacity of baking only one at a time.

6.2.2 With 3 bowls, 3 cake pans, and 3 mixers, naming them as 1, 2, and 3 schedules are as follows:

  • Preheat Oven

  • Mix ingredients in bowl 1 for cake 1 and fill the cake pan 1 with the ingredients in bowl 1 and bake cake 1.

  • Mix ingredients in bowl 1 for cake 2 and fill the cake pan 1 with the ingredients in bowl 1 and bake cake 2.

  • Mix ingredients in bowl 1 for cake 3 and fill the cake pan 1 with the ingredients in bowl 1 and bake cake 3.

  • Finish baking cake 3 and empty the pan 1

6.2.3 In the given case, all three cakes can be baked parallelly. Time is taken to bake all the cakes will be the same.

6.2.4 The loop computation is compared to the steps involved to make one cake. Multiple processors are given so that the instructions can be executed parallelly.

Data level parallelism occurs when loop iterations are independent.

Task level parallelism includes any instructions that can be computed on parallel execution units, are similar to the independent operations involved in making multiple cakes.

Step by step solution

01

Determine parallelism and its types.

In multicore and multiprocessors, parallel computing will allow several processors simultaneously execute multiple processes. The primary purpose of the parallel processing system is to enhance the processing capability and increase throughput. There are four types of parallelism bit-level parallelism, instruction level, task parallelism, and data-level parallelism.

02

Determine the schedule to make three cakes as quickly as possible.

6.2.1 The schedule for making three cakes as quickly as possible:

  • Preheat the Oven

  • Mix ingredients in a bowl for Cake 1

  • Fill the cake pan with the contents of the bowl and bake Cake 1. Meanwhile, mix the ingredients for Cake 2 in a bowl.

  • After cake 1 is baked, empty the cake pan. Fill the cake pan with the ingredients for cake 2 and bake cake 2. Meanwhile, mix the ingredients for Cake 3 in a bowl.

  • After cake 2 is baked, empty the cake pan. Fill the cake pan with the ingredients for cake 3 and bake cake 3.

  • Finish baking cake 3 and empty the cake pan.

The bottleneck of this task is having one oven with the capacity of baking only one at a time.

03

Determine the schedule to make three cakes as quickly as possible with additional resources.

6.2.2 With 3 bowls, 3 cake pans, and 3 mixers, naming them as 1, 2, and 3 schedules are as follows:

  • Preheat Oven

  • Mix ingredients in bowl 1 for cake 1 and fill the cake pan 1 with the ingredients in bowl 1 and bake cake 1.

  • Mix ingredients in bowl 1 for cake 2 and fill the cake pan 1 with the ingredients in bowl 1 and bake cake 2.

  • Mix ingredients in bowl 1 for cake 3 and fill the cake pan 1 with the ingredients in bowl 1 and bake cake 3.

  • Finish baking cake 3 and empty the pan 1

Here all the additional resources are involving preparation alone. Since we have only one oven with limited capacity. So additional resources will not provide any better performance.

04

Determine the schedule to make three cakes as quickly as possible with a large oven that can accommodate all three cakes

6.2.3 In the given case, all three cakes can be baked parallelly. Time is taken to bake all the cakes will be the same.

The schedule will be rewritten as,

  • Preheat Oven

  • Mix ingredients in bowl 1 for cake 1 and fill the cake pan 1 with the ingredients in bowl 1 and bake cake 1

  • Mix ingredients in bowl 2 for cake 2 and fill the cake pan 2 with the ingredients in bowl 2 and bake cake 2.

  • Mix ingredients in bowl 3 for cake 3 and fill the cake pan 3 with the ingredients in bowl 3 and bake cake 3.

  • Finish baking three cakes and empty all the pans parallelly.

05

Determine data-level parallelism and task-level parallelism in the cake-making loop.

6.2.4

The loop computation is compared to the steps involved to make one cake. Multiple processors are given so that the instructions can be executed parallelly.

For three cakes it takes three separate loops to bake and each step is dependent on the other. Likewise, in loop computation, the instructions may have dependencies on prior instructions in the loop body.

Data level parallelism occurs when loop iterations are independent.

Task level parallelism includes any instructions that can be computed on parallel execution units, are similar to the independent operations involved in making multiple cakes

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Most popular questions from this chapter

B.21 [10] <§§B.3, B.4> Given the following logic diagram for an accumulator, write down the Verilog module implementation of it. Assume a positive edge triggered register and asynchronous Rst.

Assume a quad-core computer system can process database queries at a steady state rate of requests per second. Also assume that each transaction takes, on average, a fixed amount of time to process. The following table shows pairs of transaction latency and processing rate.

Average Transaction Latency

Minimum transaction processing rate

1 ms

5000/sec

2 ms

5000/sec

1 ms

10,000/sec

2 ms

10,000/sec

For each of the pairs in the table, answer the following questions:

(6.20.1) On average, how many requests are being processed at any given instant?

(6.20.2) If move to an 8-core system, ideally, what will happen to the system throughput (i.e., how many queries/second will the computer process)?

(6.20.3) Discuss why we rarely obtain this kind of speedup by simply increasing the number of cores.

B.23 [20] <§§B3, B.4, B.5> Repeat Exercise B.22, but for an unsigned divider rather than a multiplier.

Question: 6.18 When performing computations on sparse matrices, latency in the memory hierarchy becomes much more of a factor. Sparse matrices lack the spatial locality in the data stream typically found in matrix operations. As a result, new matrix representations have been proposed. One the earliest sparse matrix representations is the Yale Sparse Matrix Format. It stores an initial sparse m × n matrix, M in row form using three one-dimensional arrays. Let R be the number of nonzero entries in M. We construct an array A of length R that contains all nonzero entries of M (in left -to-right top-to-bottom order). We also construct a second array IA of length m + 1 (i.e., one entry per row, plus one). IA(i) contains the index in A of the first nonzero element of row i. Row i of the original matrix extends from A(IA(i)) to A(IA(i+1)−1). The third array, JA, contains the column index of each element of A, so it also is of length R.

6.18.1 [15] consider the sparse matrix X below and write C code that would store this code in Yale Sparse Matrix Format.

Row 1 [1, 2, 0, 0, 0, 0]

Row 2 [0, 0, 1, 1, 0, 0]

Row 3 [0, 0, 0, 0, 9, 0]

Row 4 [2, 0, 0, 0, 0, 2]

Row 5 [0, 0, 3, 3, 0, 7]

Row 6 [1, 3, 0, 0, 0, 1]

6.18.2 [10] In terms of storage space, assuming that each element in matrix X is single precision floating point, compute the amount of storage used to store the Matrix above in Yale Sparse Matrix Format.

6.18.3 [15] Perform matrix multiplication of Matrix X by Matrix Y shown below. [2, 4, 1, 99, 7, 2] Put this computation in a loop, and time its execution. Make sure to increase the number of times this loop is executed to get good resolution in your timing measurement. Compare the runtime of using a naïve representation of the matrix, and the Yale Sparse Matrix Format.

6.18.4 [15] Can you find a more efficient sparse matrix representation (in terms of space and computational overhead)?

We would like to execute the loop below as efficiently as possible. We have two different machines, a MIMD machine and a SIMD machine.

for (i=0;i<2000;i++)

for(j=0;j<3000;j++)

X_array[i][j] = Y_array[j][i] + 200;

6.11.1 [10] For a 4 CPU MIMD machine, show the sequence of MIPS instructions that you would execute on each CPU. What is the speedup for this MIMD machine?

6.11.2 [10] For an 8-wide SIMD machine (i.e.,8 parallel SIMD functional units), write an assembly program in using your own SIMD extensions to MIPS to execute the loop. Compare the number of instructions executed on the SIMD machine to MIMD machine.

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