Question

Question: 6.19 In future systems, we expect to see heterogeneous computing platforms constructed out of heterogeneous CPUs. We have begun to see some appear in the embedded processing market in systems that contain both floating point DSPs and a microcontroller CPUs in a multichip module package. Assume that you have three classes of CPU: CPU A—A moderate speed multi-core CPU (with a floating point unit) that can execute multiple instructions per cycle. CPU B—A fast single-core integer CPU (i.e., no floating point unit) that can execute a single instruction per cycle. CPU C—A slow vector CPU (with floating point capability) that can execute multiple copies of the same instruction per cycle. 6.16 Exercises 573 574 Chapter 6 Parallel Processors from Client to Cloud Assume that our processors run at the following frequencies: CPU A CPU B CPU C 1 GHz 3 GHz 250 MHz CPU A can execute 2 instructions per cycle, CPU B can execute 1 instruction per cycle, and CPU C can execute 8 instructions (though the same instruction) per cycle. Assume all operations can complete execution in a single cycle of latency without any hazards. All three CPUs have the ability to perform integer arithmetic, though CPU B cannot perform floating point arithmetic. CPU A and B have an instruction set similar to a MIPS processor. CPU C can only perform floating point add and subtract operations, as well as memory loads and stores. Assume all CPUs have access to shared memory and that synchronization has zero cost. The task at hand is to compare two matrices X and Y that each contain 1024 × 1024 floating point elements. The output should be a count of the number indices where the value in X was larger or equal to the value in Y.

6.19.1 [10] Describe how you would partition the problem on the 3 different CPUs to obtain the best performance.

6.19.2 [10] What kind of instruction would you add to the vector CPU C to obtain better performance?

Short answer

6.19.1

The required code for the partitioning way of the mentioned problem:

if (x[i][j] < y[i][j])

count=count+1;

6.19.2

As the processor (vector) haven’t any kind of instructions for comparisons, so it is needed to perform (CPU-A) the two conditional jumps that are parallel completely depending on the register of floating-point.

Step-by-step solution

Define the concept.

6.19.1

This line “if (x[i][j] < y[i][j])” is used for checking if x[i][j] is greater than the y[i][j].

If the above condition is true then this line “count=count+1” will be executed and the purpose of this line is to increment the count value by one.

6.19.2

Given that the “x” and “y” are two matrices that can able to contain1024 × 1024 floating-point elements.

It is needed to utilize the CPU-C processor (the vector) for issuing the two required loads.

Determine the calculation.

6.19.1

The required code for the partitioning way of the mentioned problem:

if (x[i][j] < y[i][j]) // for checking the condition

count=count+1; // if the above condition is satisfied the count value increases.

6.19.2

The eight elements of the matrix are in the form of parallel from “A” and also the eight elements of the matrix are in the form of parallel from “B” to the one register (vector).

After that, the subtraction of the vector will be performed.

Then it is needed to issue the store of two vectors for putting the outcomes to the memory storage.

As the processor (vector) haven’t any kind of instructions for comparisons, so it is needed to perform (CPU-A) the two conditional jumps that are parallel completely depending on the register of floating-point.

Hence, two counts are incremented depending on the comparison of conditions.

After all, it can be possible to add the required two counts for the specified two matrices without using the core B.