Warning: foreach() argument must be of type array|object, bool given in /var/www/html/web/app/themes/studypress-core-theme/template-parts/header/mobile-offcanvas.php on line 20

Chapter 6: Appendix B, 28 (page 500)

B.28 [10] <§B.6> Now calculate the relative performance of adders. Assume that hardware corresponding to any equation containing only OR or AND terms, such as the equations for pi and gi on page B-40, takes one time unit T. Equations that consist of the OR of several AND terms, such as the equations for c1, c2, c3, and c4 on page B-40, would thus take two time units, 2T. The reason is it would take T to produce the AND terms and then an additional T to produce the result of the OR. Calculate the numbers and performance ratio for 4-bit adders for both ripple carry and carry lookahead. If the terms in equations are further defined by other equations, then add the appropriate delays for those intermediate equations, and continue recursively until the actual input bits of the adder are used in an equation. Include a drawing of each adder labeled with the calculated delays and the path of the worst-case delay highlighted.

Short Answer

Expert verified

The relative performance of this adder:

Sum

Delay

Carry

Delay

S3

14

C4

19

Step by step solution

01

Define the concept.

The 4- bit adderhas the feature of carry propagating and carry generating.

For the carry propagating, the carry propagator (P) is used for propagating to the following state of this.

For carry generating, the carry generator (G) is used for generating the result query by not considering the carry of the input.

The computed sum of every 4-bit adder is represented by “S”.

T time is taken for producing the AND terms.

2T time is taken for each bit in the previous adder.

Hence the total required time is 8T, where “T” denotes the unit of time.

The relative performance of this adder:

Sum

Sn-1 [n represents the number of bit in adder]

Delay

4n-2 [n represents the number of bit in adder]

Carry

Cn[n represents the number of bit in adder]

Delay

4n+3 [n represents the number of bit in adder]

02

Determine the calculation.

Relative performance of this adder:

Sum

Delay

Carry

Delay

Sn-1= S4-1= S3

4n-2 =( 4x4)-2 = 16-2 = 14

Cn = C4

4n+3 = (4X4)+3 = 16+3 = 19

In the below mentioned figure-

  • A0 and B0 are the two inputs for the first 1 bit adder.
  • A1 and B1 are the two inputs for the second 1 bit adder.
  • A2 and B2 are the two inputs for the third 1-bit adder.
  • A3 and B3 are the two inputs for the fourth 1-bit adder.
  • C0 is the “carry” for the first 1-bit adder.
  • C1 is the “carry” for the second 1-bit adder.
  • C2 is the “carry” for the third 1-bit adder.
  • C3 is the “carry” for the fourth 1-bit adder.
  • The “super” propagates are P3, P2, P1, and P0.
  • The “super” generator are G3, G2, G1, and G0.

The diagram of 4-bit adders with carry look ahead:

In the below mentioned figure-

  • C0 is the “carry” for the first 1-bit adder.
  • C1 is the “carry” for the second 1-bit adder.
  • C2 is the “carry” for the third 1-bit adder.
  • C3 is the “carry” for the fourth 1-bit adder.
  • A0 and B0 are the two inputs for the first 1-bit adder.
  • A1 and B1 are the two inputs for the second 1-bit adder.
  • A2 and B2 are the two inputs for the third 1-bit adder.
  • A3 and B3 are the two inputs for the fourth 1-bit adder.
  • The “super” propagates are P3, P2, P1, and P0.
  • The “super” generator are G3, G2, G1, and G0.

The diagram of 4-bit adders with ripple carry:

T time is taken for producing the AND terms.

2T time is taken for the each bit in the previous adder.

Hence the total required time is 8T, where “T” denotes the unit of time.

And the total required time for the adder by using “And” terms = (4x1T) =4T.

Ratio is4×2T:4×1T=8T:4T=2:1

Unlock Step-by-Step Solutions & Ace Your Exams!

  • Full Textbook Solutions

    Get detailed explanations and key concepts

  • Unlimited Al creation

    Al flashcards, explanations, exams and more...

  • Ads-free access

    To over 500 millions flashcards

  • Money-back guarantee

    We refund you if you fail your exam.

Over 30 million students worldwide already upgrade their learning with Vaia!

One App. One Place for Learning.

All the tools & learning materials you need for study success - in one app.

Get started for free

Most popular questions from this chapter

Question Title: Q2E

Question:You are trying to bake 3 blueberry pound cakes. Cake ingredients are as follows:

1 cup butter, softened

1 cup sugar

4 large eggs

1 teaspoon vanilla extract

1/2 teaspoon salt

1/4 teaspoon nutmeg

1 1/2 cups flour

1 cup blueberries

The recipe for a single cake is as follows:

Step 1: Preheat oven to 325°F (160°C). Grease and flour your cake pan.

Step 2: In large bowl, beat together with a mixer of butter and sugar at medium speed until light and fluffy. Add eggs, vanilla, salt, and nutmeg. Beat until thoroughly blended. Reduce mixer speed to low and add flour, 1/2 cup at a time, beating just until blended.

Step 3: Gently fold in blueberries. Spread evenly in a prepared baking pan. Bake for 60 minutes.

6.2.1 Your job is to cook 3 cakes as efficiently as possible. Assuming that you only have one oven large enough to hold one cake, one large bowl, one cake pan, and one mixer, come up with a schedule to make three cakes as quickly as possible. Identify the bottlenecks in completing this task.

6.2.2 Assume now that you have three bowls, 3 cake pans, and 3 mixers. How much faster is the process now that you have additional resources?

6.2.3 Assume now that you have two friends that will help you cook, and that you have a large oven that can accommodate all three cakes. How will this change the schedule you arrived at in Exercise 6.2.1 above?

6.2.4 Compare the cake-making task to computing 3 iterations of a loop on a parallel computer. Identify data-level parallelism and task-level parallelism in the cake-making loop.

Prove that a two-input multiplexor is also universal by showing how to build the NAND (or NOR) gate using a multiplexor

Derive the product-of-sums representation for Eshown on page B-11 starting with the sum-of-products representation. You will need to use DeMorgan’s theorems.

AMD has recently announced that they will be integrating a graphics processing unit with their x86 cores in a single package, though with different clocks for each of the cores. This is an example of a heterogeneous multiprocessor system which we expect to see produced commercially in the near future. One of the key design points will be to allow for fast data communication between the CPU and the GPU. Presently communications must be performed between discrete CPU and GPU chips. But this is changing in AMDs Fusion architecture. Presently the plan is to use multiple (at least 16) PCI express channels for facilitate intercommunication. Intel is also jumping into this arena with their Larrabee chip. Intel is considering to use their QuickPath interconnect technology.

6.15.1Compare the bandwidth and latency associated with these two interconnect technologies.

A.8 [5] Using SPIM, write and test a program that reads in a positive integer using the SPIM system calls. If the integer is not positive, the program should terminate with the message “Invalid Entry”; otherwise the program should print out the names of the digits of the integers, delimited by exactly one space. For example, if the user entered “728,” the output would be “Seven Two Eight.”

See all solutions

Recommended explanations on Computer Science Textbooks

View all explanations

What do you think about this solution?

We value your feedback to improve our textbook solutions.

Study anywhere. Anytime. Across all devices.

Sign-up for free