Question

B.23 [20] <§§B3, B.4, B.5> Repeat Exercise B.22, but for an unsigned divider rather than a multiplier.

Short answer

The Verilog implementation for the specified unit:

Module_divisor (s, clock, clear, B_in,Q_{in ,}W, Y, Z, B) //the parameters are s, clock, clear, B_{in ,}Q_{in ,}W, Y, Z, B

Input s, clock, clear Input [4:0] Q_in, B_in; //Q_in, B_inare two inputs

Output [4:0] Y,Z; Output [2:0] B;

System registers reg C;

reg [4:0] Y, Z, B;

reg [2:0] B;

reg [2:0] state_P, state_N ;

// combinational circuit wire z;

// state register process for controller

Always begin

assign z=|B;

if state_P<= T0;

else state_P<= state_N

end

Step-by-step solution

Define the concept.

This basically represents the Verilog implementation. This unit is also a 32-bit divisor.

This can able to perform only those operations where bits occupied by the two operands and output are less than 32 bit.

 Determine the calculation.

The process of using this unit for building a 32-bit divisor:

In the below-mentioned code, two states ( ) are assigned to reg[2:0].

//state transition process for controller

Always begin //start the loop1

Case () // for the case of and start the loop2

T₀: if = T₁; else = T₀ // for T_0,if is T₁ else will be T₀

T₁: = T₂; // for T_1, is initialized as T₂

T₂: = T₃; // for T_2, is initialized as T₃

T₃: if (z) = T0; else = T₂// for T_3,if is T₁ else will be T₂

Endcase //end of loop2

End //end of loop1