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Chapter 6: Appendix B, 21 (page 500)

B.21 [10] <§§B.3, B.4> Given the following logic diagram for an accumulator, write down the Verilog module implementation of it. Assume a positive edge triggered register and asynchronous Rst.

Short Answer

Expert verified

The required Verilog module implementation:

module_verilog_accumulator(QIn, L0, Clock, RESET, L1, Qout);

input[15:0] L0, QIn;

inputClock, RESET, L1;

Qoutput[15:0] Qout t;

reg[15:0] Qout;

always@(posedge RESET or posedge Clock) begin

if(RESET) Qout <=0;

elseif (L1)

Qout<=L0;

else

Qout<= Qout + QIn;

end

End_module_verilog_accumulator

Step by step solution

01

Define the concept of the implementation.

It is assumed in the above implementation that there is also a register of positive edge-triggered and Reset of asynchronous are present.

The above implementation is corresponding to the mentioned logic diagram.

Two loads are used in the above implementation- “LO” and “L1”.

Reset is acted like “Rst” and clock is also acted like “clk”. Qin and Qout are acted like “In” and “out” respectively.

02

 Determine the implementation with comment.

module_verilog_accumulator(QIn, L0, Clock, RESET, L1, Qout);

input[15:0] L0, QIn;

inputClock, RESET, L1;

Qoutput[15:0] Qout t;

reg[15:0] Qout;

// initialized the state for the required accumulator

always@(posedge RESET or posedge Clock) begin

// checking for the condition for RESET with “if”

if(RESET) Qout <=0;

// checking for the condition for L1 with “if”

elseif (L1)

Qout<=L0;

// When the condition of “if” statement becomes false

else

Qout<= Qout + QIn;

end

// end of the required module

End_module_verilog_accumulator

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Most popular questions from this chapter

Assume a quad-core computer system can process database queries at a steady state rate of requests per second. Also assume that each transaction takes, on average, a fixed amount of time to process. The following table shows pairs of transaction latency and processing rate.

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