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Chapter 6: Appendix B, 13 (page 500)

Assume that X consists of 3 bits, x2 x1 x0, and Y consists of 3 bits, y2 y1 y0. Write logic functions that are true if and only if

■X<Y , where X and Y are thought of as unsigned binary numbers

■ X<Y , where X and Y are thought of as signed (two’s complement) numbers

■ X = Y

Use a hierarchical approach that can be extended to larger numbers of bits. Show how can you extend it to 6-bit comparison.

Short Answer

Expert verified

The Logic function that are true if and only if

  • X<Y , where X and Y are unsigned binary numbers, let the equation be E1.

E1=x2¯.y2+(x2y2).(x1¯.y1)+(x2y2).(x1y1).(x0¯.y0)

  • X<Y , where X and Y are signed numbers

E2=x2.y2¯+(x2y2).x1¯.y1+(x2.y2).(x1y1).(x0¯.y0)

  • X = Y

E3=x2y2.(x1y1)x0y0

Step by step solution

01

Determine the logical gates and the functions

The logical functions are the combinations of the inputs and outputs of the truth table. The inputs be operated through the logical operators and the outputs are processed. Each Boolean expression can be represented through gates and the combinational circuits. The logical functions or expressions can be written from the conditions of the input and the output provided.

02

Determine the logic functions

Given, that X consist of three bits x2, x1, x0 and Y consists of three bits y2, y1, y0.

The logic functions should be written in way that are true if and only if

X<Y , where X and Y are thought of as unsigned binary numbers

X<Y , where X and Y are thought of as signed (two’s complement) numbers

X=Y

First, the 1-bit comparison will be made as follows:

The truth tables for these conditions are as follows:

X<Y

X>Y

X=Y

For X<Y

X

Y

0

0

0

0

1

1

1

0

0

1

1

0

X<Y=X¯.Y

For X>Y

X

Y

0

0

0

0

1

0

1

0

1

1

1

0

X>Y=X.Y¯

For X = Y

X

Y

0

0

1

0

1

0

1

0

0

1

1

1

X=Y=XY

From the above conditions, the logical equations can be derived.

, where X and Y are thought of as unsigned binary numbers

For an unsigned binary number, any of the following conditions must be satisfied.

Hence, the logical function is:

The logical network:

By the hierarchical approach, the 6 bit extension is as follows:

, where X and Y are thought of as signed (two’s complement) numbers

For signed binary number, any of the following conditions must be satisfied.

Hence, the logical function is:

The logical network:

By the hierarchical approach, the 6 bit extension is as follows:

,

The logical function is,

The logical network is shown below:

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Most popular questions from this chapter

Implement the four-input odd-parity function with a PLA.

Consider the following portions of two different programs running at the same time on four processors in a symmetric multi-core processor (SMP). Assume that before this code is run, both x and y are 0.

Core 1: x = 2;

Core 2: y = 2;

Core 3: w = x + y + 1;

Core 4: z = x + y;

6.7.1 [10] What are all the possible resulting values of w, x, y, and z? For each possible outcome, explain how we might arrive at those values. You will need to examine all possible interleaving’s of instructions

6.7.2 [5] How could you make the execution more deterministic so that only one set of values is possible?

A.3 Is it ever safe for a user program to use registers \(k0 or \)k1?

A.8 [5] Using SPIM, write and test a program that reads in a positive integer using the SPIM system calls. If the integer is not positive, the program should terminate with the message “Invalid Entry”; otherwise the program should print out the names of the digits of the integers, delimited by exactly one space. For example, if the user entered “728,” the output would be “Seven Two Eight.”

Question: 6.19 In future systems, we expect to see heterogeneous computing platforms constructed out of heterogeneous CPUs. We have begun to see some appear in the embedded processing market in systems that contain both floating point DSPs and a microcontroller CPUs in a multichip module package. Assume that you have three classes of CPU: CPU A—A moderate speed multi-core CPU (with a floating point unit) that can execute multiple instructions per cycle. CPU B—A fast single-core integer CPU (i.e., no floating point unit) that can execute a single instruction per cycle. CPU C—A slow vector CPU (with floating point capability) that can execute multiple copies of the same instruction per cycle. 6.16 Exercises 573 574 Chapter 6 Parallel Processors from Client to Cloud Assume that our processors run at the following frequencies: CPU A CPU B CPU C 1 GHz 3 GHz 250 MHz CPU A can execute 2 instructions per cycle, CPU B can execute 1 instruction per cycle, and CPU C can execute 8 instructions (though the same instruction) per cycle. Assume all operations can complete execution in a single cycle of latency without any hazards. All three CPUs have the ability to perform integer arithmetic, though CPU B cannot perform floating point arithmetic. CPU A and B have an instruction set similar to a MIPS processor. CPU C can only perform floating point add and subtract operations, as well as memory loads and stores. Assume all CPUs have access to shared memory and that synchronization has zero cost. The task at hand is to compare two matrices X and Y that each contain 1024 × 1024 floating point elements. The output should be a count of the number indices where the value in X was larger or equal to the value in Y.

6.19.1 [10] Describe how you would partition the problem on the 3 different CPUs to obtain the best performance.

6.19.2 [10] What kind of instruction would you add to the vector CPU C to obtain better performance?

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