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Chapter 6: Appendix B, 12. (page 500)

Implement the four functions described in Exercise B.11 using a PLA

Short Answer

Expert verified

X contains only one 0:

X=.x2.x1.x0+x2..x1.x0+x2.x1..x0

X contains an even number of zero

X=.x2..x1.x0+.x2.x1..x0+x2..x1..x0

X interpreted as an unsigned binary number less than 4

Y=.x2

X interpreted as a negative number

Step-by-Step Solution

Step by step solution

01

Determine the logical gates

The PLA is the programmable logical array that is used to illustrate the logical circuits, The basic logic gates are AND, OR, and NOT. AND gate will take two inputs and produce output as 1 only if both the inputs are 1. OR gate will take two inputs and produce output 1 if any of the inputs is 1. NOT gate will take only one input and gives the opposite of the input as the output. 1.

02

Determine the logic functions

Given that the X consists of 3 bits x0, x1, and x2. The logic functions for which that are true if and only if

  • X contains only one 0
  • X contains an even number of 0s
  • X when interpreted as an unsigned binary number is less than 4
  • X when interpreted as a signed (two’s complement) number is negative.

For X contains only one zero, only one of the three bits should be zero. The logical function that satisfies this condition is as follows:

The logical circuit is as follows:

For X contains an even number of 0s, two bits of the three bits should be zero. The logical function that satisfies this condition is as follows:

The logical circuit is as follows:

For X when interpreted as an unsigned binary number is less than 4 is as follows:

The logical circuit is as follows:

ForX when interpreted as a signed (two’s complement) number is negative. The values will be complements and the logical function is as

The logical circuit is as follows:

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Most popular questions from this chapter

Question: Consider the following portions of two different programs running at the same time on four processors in a symmetric multi-core processor (SMP). Assume that before this code is run, both x and y are 0.

Core 1: x = 2;

Core 2: y = 2;

Core 3: w = x + y + 1;

Core 4: z = x + y;

6.7.1 [10] What are all the possible resulting values of w, x, y, and z? For each possible outcome, explain how we might arrive at those values. You will need to examine all possible interleaving’s of instructions

6.7.2 [5] How could you make the execution more deterministic so that only one set of values is possible?

We would like to execute the loop below as efficiently as possible. We have two different machines, a MIMD machine and a SIMD machine.

for (i=0;i<2000;i++)

for(j=0;j<3000;j++)

X_array[i][j] = Y_array[j][i] + 200;

6.11.1 [10] For a 4 CPU MIMD machine, show the sequence of MIPS instructions that you would execute on each CPU. What is the speedup for this MIMD machine?

6.11.2 [10] For an 8-wide SIMD machine (i.e.,8 parallel SIMD functional units), write an assembly program in using your own SIMD extensions to MIPS to execute the loop. Compare the number of instructions executed on the SIMD machine to MIMD machine.

Question: Many computer applications involve searching through a set of data and sorting the data. A number of efficient searching and sorting algorithms have been devised in order to reduce the runtime of these tedious tasks. In this problem we will consider how best to parallelize these tasks.

(6.3.1) Consider the following binary search algorithm (a classic divide and conquer algorithm) that searches for a value X in a sorted N-element array A and returns the index of matched entry:

BinarySearch(A[0..N-1], X) {

low=0

high=N-1

while(low<high) {

mid=(low<=high). {

mid = (low+high)/2

if (A[mid]>X)

high = mid -1

else if (A[mid]<X)

low=mid+1

else

return mid //found

}

return -1 //not found

}

Assume that you have Y cores on a multi-core processor to run BinarySearch. Assuming that Y is much smaller than N, express the speedup factor you might expect to obtain for values of Y and N. Plot these on a graph.

(6.3.2) Next, assume that Y is equal to N. How would this affect your conclusions in your previous answer? If you were tasked with obtaining the best speedup factor possible (i.e. strong scaling), explain how you might change this code to obtain it.

AMD has recently announced that they will be integrating a graphics processing unit with their x86 cores in a single package, though with different clocks for each of the cores. This is an example of a heterogeneous multiprocessor system which we expect to see produced commercially in the near future. One of the key design points will be to allow for fast data communication between the CPU and the GPU. Presently communications must be performed between discrete CPU and GPU chips. But this is changing in AMDs Fusion architecture. Presently the plan is to use multiple (at least 16) PCI express channels for facilitate intercommunication. Intel is also jumping into this arena with their Larrabee chip. Intel is considering to use their QuickPath interconnect technology.

6.15.1Compare the bandwidth and latency associated with these two interconnect technologies.

Assume we want to execute the DAXPY loop show on page 511 in MIPS assembly on the NVIDIA 8800 GTX GPU described in this chapter. In this problem, we will assume that all math operations are performed on single-precision floating point numbers (we will rename the loop SAXPY). Assume that instructions take the following number of cycles to execute.

Loads

Stores

Add.S

Mult.S

5

2

3

4

6.13.1Describe how you will constructs warps for the SAXPY loop to exploit the 8 cores provided in a single multiprocessor.

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