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Chapter 6: Appendix A, 1. (page 500)

A.1 [5] Section A.5 described how memory is partitioned on most MIPS systems. Propose another way of dividing memory that meets the same goals.

Short Answer

Expert verified

The other way of dividing memory is to exchange the memory spaces.

Step by step solution

01

Memory Partition in MIPS.

The MIPS processor's assembly language is simply known as MIPS assembly language. MIPS is an acronym for Microprocessor without Interlocked Pipeline Stages. Every system works on the MIPS processor typically divides the memory into three parts. The first part is at the bottom of the address space which is also called a text segment. The segment above the text segment is also called a data segment. The data segment is further divided into two parts which are static data and dynamic data. The lifetime and size of the data stored in static data are already known by the compiler. The other part of the data segment is dynamic data which implies its name and the variables which can change the data size during the execution of the program. The final segment is the stack segment, as the program pushes values on the stack, the operating system expands its stack toward the data segment and decides which segment that data should fall. Most of the convictions mentioned are not practically implemented the hardware rather these are the limitations set by the programmer to use the MIPS architecture effectively.

The partition of the memory using MIPS looks as follows:

02

Ideal way for Dividing Memory in MIPS

Here one of the possible ways would be to exchange the memories spaces for those two segments since the two dynamically data segments should be as far as possible, shift the complete data segment to the stack segment and the stack segment is moved to the data segment.

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Most popular questions from this chapter

Question Title: Q2E

Question:You are trying to bake 3 blueberry pound cakes. Cake ingredients are as follows:

1 cup butter, softened

1 cup sugar

4 large eggs

1 teaspoon vanilla extract

1/2 teaspoon salt

1/4 teaspoon nutmeg

1 1/2 cups flour

1 cup blueberries

The recipe for a single cake is as follows:

Step 1: Preheat oven to 325°F (160°C). Grease and flour your cake pan.

Step 2: In large bowl, beat together with a mixer of butter and sugar at medium speed until light and fluffy. Add eggs, vanilla, salt, and nutmeg. Beat until thoroughly blended. Reduce mixer speed to low and add flour, 1/2 cup at a time, beating just until blended.

Step 3: Gently fold in blueberries. Spread evenly in a prepared baking pan. Bake for 60 minutes.

6.2.1 Your job is to cook 3 cakes as efficiently as possible. Assuming that you only have one oven large enough to hold one cake, one large bowl, one cake pan, and one mixer, come up with a schedule to make three cakes as quickly as possible. Identify the bottlenecks in completing this task.

6.2.2 Assume now that you have three bowls, 3 cake pans, and 3 mixers. How much faster is the process now that you have additional resources?

6.2.3 Assume now that you have two friends that will help you cook, and that you have a large oven that can accommodate all three cakes. How will this change the schedule you arrived at in Exercise 6.2.1 above?

6.2.4 Compare the cake-making task to computing 3 iterations of a loop on a parallel computer. Identify data-level parallelism and task-level parallelism in the cake-making loop.

Question: 6.16 Refer to Figure 6.14b, which shows an n-cube interconnect topology of order 3 that interconnects 8 nodes. One attractive feature of an n-cube interconnection network topology is its ability to sustain broken links and still provide connectivity.

6.16.1 [10] Develop an equation that computes how many links in the n-cube (where n is the order of the cube) can fail and we can still guarantee an unbroken link will exist to connect any node in the n-cube. 6.16.2 [10] Compare the resiliency to failure of n-cube to a fully-connected interconnection network. Plot a comparison of reliability as a function of the added number of links for the two topologies.

We would like to execute the loop below as efficiently as possible. We have two different machines, a MIMD machine and a SIMD machine.

for (i=0;i<2000;i++)

for(j=0;j<3000;j++)

X_array[i][j] = Y_array[j][i] + 200;

6.11.1 [10] For a 4 CPU MIMD machine, show the sequence of MIPS instructions that you would execute on each CPU. What is the speedup for this MIMD machine?

6.11.2 [10] For an 8-wide SIMD machine (i.e.,8 parallel SIMD functional units), write an assembly program in using your own SIMD extensions to MIPS to execute the loop. Compare the number of instructions executed on the SIMD machine to MIMD machine.

A systolic array is an example of an MISD machine. A systolic array is a pipeline network or “wavefront” of data processing elements. Each of these elements does not need a program counter since execution is triggered by the arrival of data. Clocked systolic arrays compute in “lock-step” with each processor undertaking alternate compute and communication phases.

6.12.1 [10] Consider proposed implementations of a systolic array (you can find these in on the internet or in technical publications). Then attempt to program the loop provided in Exercise 6.11 using this MISD model. Discuss any difficulties you encounter.

6.12.2 [10] Discuss the similarities and differences between an MISD and SIMD machine. Answer this question in terms of data-level parallelism.

A.7 [5] Using SPIM, write and test a program that reads in three integers and prints out the sum of the largest two of the three. Use the SPIM system calls described on pages A-43 and A-45. You can break ties arbitrarily.

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