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AMD has recently announced that they will be integrating a graphics processing unit with their x86 cores in a single package, though with different clocks for each of the cores. This is an example of a heterogeneous multiprocessor system which we expect to see produced commercially in the near future. One of the key design points will be to allow for fast data communication between the CPU and the GPU. Presently communications must be performed between discrete CPU and GPU chips. But this is changing in AMDs Fusion architecture. Presently the plan is to use multiple (at least 16) PCI express channels for facilitate intercommunication. Intel is also jumping into this arena with their Larrabee chip. Intel is considering to use their QuickPath interconnect technology.

6.15.1Compare the bandwidth and latency associated with these two interconnect technologies.

Short Answer

Expert verified

6.15.1

AMD:

Bandwidth: 42 GB/s

Latency: about 12ns

Intel QuickPath

Bandwidth: about 25.6 GB/s

Latency: about 12ns

From the data, AMD Fusion seems to be better as the open end technology, still QuickPath outrages AMD in optimization.

Step by step solution

01

Determine AMD fusion and Intel Quickpath

AMD integrated graphical processing unit with the x86 cores in a single package, with different clock for each core. This is a heterogeneous multiprocessor system. This provides the faster data communication between CPU and GPU. Intel has introduced QuickPath interconnect technology that is the point to point system that optimizes the work as a communications between many processors.

02

Determine the bandwith and latency

6.15.1

AMD is the hyper connect that communicates faster with between CPUs and GPUs. The Intel Quick path is point-to-point technology that optimized the communication mechanisms.

AMD:

Bandwidth:

To read from local frame buffer: 17 GB/s

To write to local frame buffer: 13 GB/s

Uncached memory: 12 GB/s

Latency: about 12ns

Intel QuickPath

Bandwidth: about 25.6 GB/s

Latency: about 12ns

From the data, AMD Fusion seems to be better as the open end technology, still QuickPath outrages AMD in optimization.

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Most popular questions from this chapter

B.21 [10] <§§B.3, B.4> Given the following logic diagram for an accumulator, write down the Verilog module implementation of it. Assume a positive edge triggered register and asynchronous Rst.

B.28 [10] <§B.6> Now calculate the relative performance of adders. Assume that hardware corresponding to any equation containing only OR or AND terms, such as the equations for pi and gi on page B-40, takes one time unit T. Equations that consist of the OR of several AND terms, such as the equations for c1, c2, c3, and c4 on page B-40, would thus take two time units, 2T. The reason is it would take T to produce the AND terms and then an additional T to produce the result of the OR. Calculate the numbers and performance ratio for 4-bit adders for both ripple carry and carry lookahead. If the terms in equations are further defined by other equations, then add the appropriate delays for those intermediate equations, and continue recursively until the actual input bits of the adder are used in an equation. Include a drawing of each adder labeled with the calculated delays and the path of the worst-case delay highlighted.

B.23 [20] <§§B3, B.4, B.5> Repeat Exercise B.22, but for an unsigned divider rather than a multiplier.

First, write down a list of the daily activities that you typically do on a weekday. For instance, you might get out of bed, take a shower, get dressed, eat breakfast, dry your hair, and brush your teeth. Make sure to break down your list so you have a minimum of 10 activities.

6.1.1 Now consider which of these activities is already exploiting some form of parallelism (e.g., brushing multiple teeth at the same time, versus one at a time, carrying one book at a time to school, versus loading them all into your backpack and then carry them “in parallel”). For each of your activities, discuss if they are already working in parallel, but if not, why they are not.

6.1.2 Next, consider which of the activities could be carried out concurrently (e.g., eating breakfast and listening to the news ). For each of your activities, describe which other activity could be paired with this activity.

6.1.3 For 6.1.2, what could we change about current systems (e.g., showers, clothes, TVs, cars) so that we could perform more tasks in parallel?

6.1.4 Estimate how much shorter time it would take to carry out these activities if you tried to carry out as many tasks in parallel as possible.

Question: Consider the following portions of two different programs running at the same time on four processors in a symmetric multi-core processor (SMP). Assume that before this code is run, both x and y are 0.

Core 1: x = 2;

Core 2: y = 2;

Core 3: w = x + y + 1;

Core 4: z = x + y;

6.7.1 [10] What are all the possible resulting values of w, x, y, and z? For each possible outcome, explain how we might arrive at those values. You will need to examine all possible interleaving’s of instructions

6.7.2 [5] How could you make the execution more deterministic so that only one set of values is possible?

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