Question

Recall that we have two write policies and write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches:

L1	L2
Write through, non-write allocate	Write back, write allocate

5.4.1 Buffers are employed between different levels of memory hierarchy to reduce access latency. For this given configuration, list the possible buffers needed between L1 and L2 caches, as well as L2 cache and memory.

5.4.2 Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.

5.4.3 For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), configuration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block

Consider the following program and cache behaviors.

Data Reads per 100 Instructions	Data writes per 1000 Instructions	Instruction Cache Miss Rate	Data Cache Miss Rate	Block Size(byte)
250	100	0.30%	2%	64%

5.4.4 For a write-through, write-allocate cache, what are the minimum read and write bandwidths (measured by byte per cycle) needed to achieve a CPI of 2?

5.4.5 For a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the minimal read and write bandwidths needed for a CPI of 2?

5.4.6 What are the minimal bandwidths needed to achieve the performance of CPI=1.5?

Short answer

5.4.1

Buffers needed between the L1 and L2 cache is write buffer

Buffer needed L2 cache and memory is write buffer

5.4.2

If the result in in L2 cache the block must be brought into the L2 cache

5.4.3

The block will reside in L2 but not in L1 if L1 write misses. The block in L2 will be required to be written back to memory if a subsequent read miss on the same block, transferred to L1, and invalidated in L2.

5.4.4

The total read bandwidth requirement is $=0.33\mathrm{bytes}/\mathrm{cycle}$

The data write bandwidth requirement = 0.2 bytes/cycle.

5.4.5

The data read bandwidth is $=0.23\mathrm{bytes}/\mathrm{cycle}$

Now, the data write bandwidth $=0.067\mathrm{bytes}/\mathrm{cycle}$

5.4.6

For the write-through cache

The total read bandwidth $=0\cdot 35\mathrm{byte}/\mathrm{cycle}$

For the write-back cache

Data write bandwidth $=0\cdot 091\mathrm{byte}/\mathrm{cycle}$

Step-by-step solution

Determine the formulae

The formula for determining the IPC

$IPC=\frac{1}{CPI}$ …….(1)

$Cyclewillrequireadataread=\frac{percentageofdatareads}{CPI}$ …….(2)

$Cyclewillrequireadatawrite=\frac{percentageofdatawrite}{CPI}$ ……..(3)

Describe write policy and write allocation policy

Write policy explains what the cache performs when the CPU sends a write request

There is two cache write methods:

a. write-through policy

b. write-back policy

Write allocation policy

A write-allocate cache is a subclass of a write-back cache that allocates new lines in the cache for writings that miss the cache, allowing the writes to reach the cache.

List the possible buffers needed between L1 and L2 caches and between L2 cache and memory.

5.4.1

The write miss penalty in the L1 cache is low, whereas the write miss penalty in the L2 cache is high.The L2 cache’s write miss latency could be hidden by a write buffer between the L1 and L2 caches

When replacing a dirty block, write buffers would be beneficial for the L2 cache, this is because A new block is read into memory before the dirty block is written to memory

Step 4: Describe the procedure of handling an L1 write-miss and the possibility of replacing a dirty block.

5.4.2

For L1 cache, there is no need to check dirty blocks according to the given condition such as non-write allocation and write through cache.

Thus, we check directly L1 cache.

Check if the block is dirty if a miss occurrence occurs on L2 cache memory.

If block is dirty then a block must be allocated to L2 cache memory and then the evicted block is written to the main memory.

Otherwise

The dirty block set and L2 cache memory are simply updated if the L2 cache memory is hit.

Describe the procedure of handling an L1 write-miss for a multilevel exclusive cache.

5.4.3

The block will reside in L2 but not in L1 if L1 write misses. The block in L2 will be required to be written back to memory if a subsequent read miss on the same block, transferred to L1, and invalidated in L2.

determine the minimum read and write bandwidths needed to achieve a CPI of 2

5.4.4

First, you must read in the block from memory into cache then write the block to cache, for write allocate or write miss. You must write one word back to memory for write-through. Reading an instruction must be included for read bandwidth. Bandwidth refers to the bandwidth of memory

Given CPI = 2

When CPI =2

then IPC (Instruction per cycle) = $\frac{1}{2}=0.5$

Cycle will require a data read=$12.5\%$

Cycle will require a data write = $5\%$

Thus, the instruction bandwidth is = $(0.0030\times 64)\times 0.5=0.096bytes/cycle$

The data read bandwidth is $=0.02\times (0.13+0.050)\times 64=0.23bytes/cycle$

The total read bandwidth requirement is $=0.33bytes/cycle$

The data write bandwidth requirement is $0.05\times 4$= 0.2 bytes/cycle.

Determine the minimal read and write bandwidths needed for a CPI of 2

5.4.5

The instruction bandwidth and the data read bandwidth is same as in step 4

The instruction bandwidth is = $(0.0030\times 64)\times 0.5=0.096bytes/cycle$

The data read bandwidth is $=0.02\times (0.13+0.050)\times 64=0.23bytes/cycle$

Now, the data write bandwidth $=0.02\times 0.30\times (0.13+0.050)\times 64$

$=0.067bytes/cycle$

Determine the minimal bandwidths needed to achieve the performance of CPI=1.5

5.4.6

Given CPI is 1.5

Instruction throughput $=\frac{1}{1\cdot 5}$

$=0.67$ instructions per cycle

Data read frequency $=\frac{0\cdot 25}{1\cdot 5}$

$=0.17$

The write frequency

role="math" localid="1655284298048" $$\begin{gathered} =\frac{0.10}{1\cdot 5} \\ =0\cdot 067 \end{gathered}$$

The instruction bandwidth $=(0\cdot 0030\times 64)\times 0\cdot 67$

$=0\cdot 35bytes/cycle$

For the write-through cache

The data read bandwidth $\begin{array}{l}=0\cdot 02\times (0\cdot 17+0\cdot 067)\times 64\\ =0\cdot 22byte/cycle\end{array}$

The total read bandwidth $=0\cdot 35byte/cycle$

Data write bandwidth $\begin{array}{l}=0\cdot 067\times 4\\ =0\cdot 27bytes/cycle\end{array}$

For the write-back cache

Data write bandwidth $\begin{array}{l}=0\cdot 02\times (0.17+0.067)\times 64\\ =0\cdot 091byte/cycle\end{array}$