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Question 2.4 [5] For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and \(s7, respectively.

sll \)t0, \(s0, 2 # \)t0 = f * 4

add \(t0, \)s6, \(t0 # \)t0 = &A[f]

sll \(t1, \)s1, 2 # \(t1 = g * 4

add \)t1, \(s7, \)t1 # \(t1 = &B[g]

lw \)s0, 0(\(t0) # f = A[f]

addi \)t2, \(t0, 4

lw \)t0, 0(\(t2)

add \)t0, \(t0, \)s0

sw \(t0, 0(\)t1)

Short Answer

Expert verified

The corresponding C code:

f = A[f];
f = A[f+1] + A[f]
B[g] = f;

Step by step solution

01

Define the concept.

The line “f = A[f]” is used for assigning the value of “A[f]” to the “f”. Then the line “f = A[f+1] + A[f]” first does the sum of “A[f+1]” and “A[f]” and then the value of the sum is assigned to the “f”. And “B[g] = f” is used for assigning the value of “f” to the “B[g]”.

02

Determine the calculation.

The corresponding C code:

f = A[f]; //Initialize the value of “A[f]” to the “f”.
f = A[f+1] + A[f] // Initialize the value of “A[f+1] + A[f]” to the “f”.
B[g] = f; // Initialize the value of “f” to the “B[g]”.

By assuming “f” and “g” are assigned to registers of “$s0”and registers of “$s1” respectively and also assuming that the base address of the “A” and “B” arrays are in registers of “$s6” and registers of “$s7”,

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Most popular questions from this chapter

For each MIPS instruction, show the value of the opcode(OP), source register(RS), and target register(RT) fields. For the I-type instructions, show the value of the immediate field, and for the R-type instructions, show the value of the destination register(RD) field.

addi \(t0,\)s6,4

add \(t1.\)s6,\(0

sw \)t1, 0(\(t0)

lw \)t0,0(\(t0)

add \)s0,\(t1,\)t0

For the following MIPS assembly instructions above, what is a corresponding C statement?

add f, g, h

add f, i, f

Question: For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and $s7, respectively.

Assume \(t0 holds the value 0x00101000. What is the value of \)t2 after the following instructions?

slt \(t2, \)0, \(t0

bne \)t2, \(0, ELSE

j DONE

ELSE: addi \)t2,$t2, 2

DONE:

Question: [5] Assume for a given processor the CPI of arithmetic instructions is 1, the CPI of load/store instructions is 10, and the CPI of branch instructions is 3.

Assume a program has the following instruction breakdowns: 500 million arithmetic instructions, 300 million load/store instructions, 100 million branch instructions.

2.46.1 [5] <§2.19> Suppose that new, more powerful arithmetic instructions are added to the instruction set. On average, through the use of these more powerful arithmetic instructions, we can reduce the number of arithmetic instructions needed to execute a program by 25%, and the cost of increasing the clock cycle time by only 10%. Is this a good design choice? Why?

2.46.2 [5] <§2.19> Suppose that we find a way to double the performance of arithmetic instructions. What is the overall speedup of our machine? What if we find a way to improve the performance of arithmetic instructions by 10 times?

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