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Question: Using your code from Exercise 2.43 as an example, explain what happens when two processors begin to execute this critical section at the same time, assuming that each processor executed exactly one instruction per cycle.

Short Answer

Expert verified

Suppose the two processors begin to execute this critical section at the same time, assuming that each processor executed exactly one instruction per cycle. In that case, the code can be executed completely without reaching SC instruction. If only one processor executes SC, then it completes successfully. If both processors reach SC in the same cycle, only one will complete, and the other will fail.

Step by step solution

01

Step 1:Determine thecritical section

The critical section will have the shared resources and variables and perform write operations on them. This can be prevented by the synchronization mechanism. Lock () and unlock() functions will prevent overriding the values and the deadlock. Lock () will lock the variable that is not allowed to other processes. Unlock() will release the variables that have been written.

02

Determinewhat happens when two processors begin to execute the critical section at the same time

MIPS code: refer 2.43 or 2.44 solution

try: ll $t0, 0($a1) #load linked will load the value from memory and monitor the memory location to check if any process performs write to it

slt $t1, $t0, $a2 #set to less than will check the values of $t0 and $a2, if $t0 is less then $a2, then $t1 will be set to 1

bnez $t1, skip # check for the value of $t1, if the value is not equal to zero , then will branch to skip function

mov $t0, $a2 # value of $a2 will be moved to $t0

sc $t0, 0($a1) #store conditionals will store the value to the memory, if there is no writes to the monitored memory address.

beqz $t0,try #Checks the value of $t0 , if the value is zero , then the branch will move to try function.

skip:

Suppose the two processors begin to execute this critical section at the same time, assuming that each processor executed exactly one instruction per cycle. In that case, the code can be executed completely without reaching SC instruction. If only one processor executes SC, then it completes successfully. If both processors reach SC in the same cycle, only one will complete, and the other will fail.

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Most popular questions from this chapter

Question: Assume that for a given program 70% of the executed instructions are arithmetic, 10% are load/store, and 20% are branch.

2.47.1 [5] <§2.19> Given this instruction mix and the assumption that an

arithmetic instruction requires 2 cycles, a load/store instruction takes 6 cycles, and a branch instruction takes 3 cycles, find the average CPI.

2.47.2 [5] <§2.19> For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

2.47.3 [5] <§2.19> For a 50% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

Question 2.4 [5] For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and \(s7, respectively.

sll \)t0, \(s0, 2 # \)t0 = f * 4

add \(t0, \)s6, \(t0 # \)t0 = &A[f]

sll \(t1, \)s1, 2 # \(t1 = g * 4

add \)t1, \(s7, \)t1 # \(t1 = &B[g]

lw \)s0, 0(\(t0) # f = A[f]

addi \)t2, \(t0, 4

lw \)t0, 0(\(t2)

add \)t0, \(t0, \)s0

sw \(t0, 0(\)t1)

For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and $s7, respectively.

B8=Ai-j;

Question [5] <§2.7> Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, i, and j are in registers \(s0, \)s1, \(t0, and \)t1, respectively. Also, assume that register $s2 holds the base address of the array D.

for(i=0; i<a; i++)

for(j=0; j<b; j++)

D[4*j] = i + j;

Question: Provide a minimal set of MIPS instructions that may be used to implement the following pseudo instruction:

not \(t1,\)t2 // bit-wise invert

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