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Question: Repeat Exercise 2.43, but this time use ll/sc to perform an atomic update of the shvar variable directly, without using lock() and unlock(). Note that in this problem there is no variable lk.

Short Answer

Expert verified

The MIPS assembly code to implement the given C code:

try: ll $t0, 0($a1)

slt $t1, $t0, $a2

bnez $t1, skip

mov $t0, $a2)

sc $t0, 0($a1)

beqz $t0,try

skip:

Step by step solution

01

Step 1:Determine theMIPS branch instructions and parallelism

Parallelism can be achieved by MIPS assembly language through a pair of special instructions. The instructions load linked and store conditional are used in sequence. If the contents of the memory location specified by the load linked are changed before the store conditional to the same address occurs, the store conditional fails.If the store conditional succeeds, it changes the value of the register to 1. Then the load linked will return the initial value. This sequence implements the atomic change on the memory location.

02

Determine the MIPS assembly code to implement the given C code.

Given C code:

lock(lk);

shvar=max(shvar.x);

unlock(lk);

It is given that: use ll/sc to perform an atomic update of the shvar variable directly, without using lock() and unlock().

MIPS code for the given C:

try: ll $t0, 0($a1) #load linked will load the value from memory and monitor the memory location to check if any process performs write to it

slt $t1, $t0, $a2 #set to less than will check the values of $t0 and $a2, if $t0 is less then $a2, then $t1 will be set to 1

bnez $t1, skip # check for the value of $t1, if the value is not equal to zero , then will branch to skip function

mov $t0, $a2 # value of $a2 will be moved to $t0

sc $t0, 0($a1) #store conditionals will store the value to the memory, if there is no writes to the monitored memory address.

beqz $t0,try #Checks the value of $t0 , if the value is zero , then the branch will move to try function.

skip:

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Most popular questions from this chapter

Question: Can we use the tail-call optimization in this function? If no, explain why not. If yes, what is the difference in the number of executed instructions in f with and without the optimization?

Question: Assume that for a given program 70% of the executed instructions are arithmetic, 10% are load/store, and 20% are branch.

2.47.1 [5] <§2.19> Given this instruction mix and the assumption that an

arithmetic instruction requires 2 cycles, a load/store instruction takes 6 cycles, and a branch instruction takes 3 cycles, find the average CPI.

2.47.2 [5] <§2.19> For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

2.47.3 [5] <§2.19> For a 50% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

For the MIPS assembly instructions in Exercise 2.4, rewrite the assembly code to minimize the number if MIPS instructions (if possible) needed to carry out the same function.

Assume that registers \(s0 and \)s1 hold the values 0x80000000 and 0xD0000000, respectively.

1. What is the value of \(t0 for the following assembly code?

add \)t0,\(s0,\)s1

2. Is the result in \(t0 the desired result, or has there been an overflow?

3. For the contents of registers \)s0 and \(s1 as specified above, what is the value of \)t0 for the following assembly code?

sub \(t0,\)s0,\(s1

4. Is the result in \)t0 the desired result, or has there been an overflow?

5. For the contents of registers \(s0 and \)s1 as specified above, What is the value of \(t0 for the following assembly code?

add \)t0,\(s0,\)s1

add \(t0,\)t0,\(s0

6. Is the result in \)t0 the desired result, or has there been an overflow?

Question: Translate into decimal.

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