Chapter 2: Q39E (page 172)
Write the MIPS assembly code that creates the 32-bit constant 0010 0000 0000 0001 0100 1001 0010 0100 and stores that value to register $t1.
The MIPS assembly code is:
lui $t1, 0x2001
ori $t1, $t1, 0x4924
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Question: Repeat Exercise 2.43, but this time use ll/sc to perform an atomic update of the shvar variable directly, without using lock() and unlock(). Note that in this problem there is no variable lk.
Assume that for a given program 70% of the executed instructions are arithmetic, 10% are load/store, and 20% are branch.
2.47.1 [5] <§2.19> Given this instruction mix and the assumption that an
arithmetic instruction requires 2 cycles, a load/store instruction takes 6 cycles, and a branch instruction takes 3 cycles, find the average CPI.
2.47.2 [5] <§2.19> For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?
2.47.3 [5] <§2.19> For a 50% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?
Question: Translate the following C code to MIPS. Assume that the variables f, g, h, i , and j are assigned to registers \(s0,\)s1,\(s2,\)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and $s7 respectively. Assume that the elements of the arrays A and B are 4 byte words:
B[8]=A[i]+A[j];
Question: Find the shortest sequence of MIPS instructions that extracts bits 16 down to 11 from register \(t0 and uses the value of this field to replace bits 31 down to 26 in register \)t1 without changing the other 26 bits of register $t1.
Question: Assume \(t0 holds the value 0x00101000. What is the value of \)t2 after the following instructions?
slt \(t2, \)0, \(t0
bne \)t2, \(0, ELSE
j DONE
ELSE: addi \)t2,$t2, 2
DONE:
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