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Question: Consider the following code:

lbu \(t0, 0(\)t1)

sw \(t0, 0(t2)

Assume that the register \)t1 contains the address and the register \(t2 contains the address

. Note the MIPS architecture utilizes big-endian addressing. Assume that the data (in hexadecimal) at the address is . What value is stored at the address pointed to by register \)t2?

Short Answer

Expert verified

The value stored at the address pointed to by register $t2 is

Step by step solution

01

Determine ASCII and Binary numbers in MIPS.

The ASCII digits are presented as strings and each digit is 8 bits long. MIPS provides the instructions to load and store bytes. The “Load byte” instruction will load the byte from the memory. The byte will be placed at the 8 extreme right bits of a register. The “Store word” instruction will take the byte from the register and write it to the memory.

02

Determine the value of $t2.

It is given that the register $t1 contains and$t2 contains .

The MIPS architecture follows a big-endian address, which means the MSB is stored first.

The data at $t1 is

The instruction lbu $t0,0($t1) will load the unsigned bytes to the 8 extreme-right bits of the address $t1.

The instruction sb $t0, 0($t2) will store the value at the specified address.

We know that is the data in $t1, now after the execution of instructions, the consecutive bytes of the word will be stored in four addresses.



Address

data

0x1000 0000

0x11

0x1000 0001

0x22

0x1000 0002

0x33

0x1000 0003

0x44

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Most popular questions from this chapter

Question: [5] Assume for a given processor the CPI of arithmetic instructions is 1, the CPI of load/store instructions is 10, and the CPI of branch instructions is 3.

Assume a program has the following instruction breakdowns: 500 million arithmetic instructions, 300 million load/store instructions, 100 million branch instructions.

2.46.1 [5] <§2.19> Suppose that new, more powerful arithmetic instructions are added to the instruction set. On average, through the use of these more powerful arithmetic instructions, we can reduce the number of arithmetic instructions needed to execute a program by 25%, and the cost of increasing the clock cycle time by only 10%. Is this a good design choice? Why?

2.46.2 [5] <§2.19> Suppose that we find a way to double the performance of arithmetic instructions. What is the overall speedup of our machine? What if we find a way to improve the performance of arithmetic instructions by 10 times?

Question: Provide a minimal set of MIPS instructions that may be used to implement the following pseudo instruction:

not \(t1,\)t2 // bit-wise invert

[5] <§2.7> Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, i, and j are in registers \(s0, \)s1, \(t0, and \)t1, respectively. Also, assume that register $s2 holds the base address of the array D.

for(i=0; i<a; i++)

for(j=0; j<b; j++)

D[4*j] = i + j;

Question: [5] Consider the following MIPS loop:

LOOP: slt \(t2, \)0, \(t1

beq \)t2, \(0, DONE

subi \)t1, \(t1, 1

addi \)s2, \(s2, 2

j LOOP

DONE:

2.26.1 [5] <§2.7> Assume that the register \)t1 is initialized to the value 10. What is the value in register \(s2 assuming \)s2 is initially zero?

2.26.2 [5] <§2.7> For each of the loops above, write the equivalent C code routine. Assume that the registers \(s1, \)s2, \(t1, and \)t2 are integers A, B, i, and temp, respectively.

2.26.3 [5] <§2.7> For the loops written in MIPS assembly above, assume that the register $t1 is initialized to the value N. How many MIPS instructions are executed?

[5] <§2.7> Suppose the program counter (PC) is set to 0x2000 0000. Is it possible to use the jump (j) MIPS assembly instruction to set the PC to the address as 0x4000 0000? Is it possible to use the branch-on-equal (beq) MIPS assembly instruction to set the PC to this same address?

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