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Question: For the following C statement, write a minimal sequence of MIPS assembly instructions that does the identical operation. Assume \(t1=A, \)t2=B and $s1 is the base address of C.


Short Answer

Expert verified

The sequence of MIPS assembly instructions for the is as follows:

lw $t3,0($s1)

sll $t1,$t3,4

Step by step solution

01

Define MIPS logical instructions and Arrays.

The sll and srl are the shift instructions that make the left and a right shift in the bits of the registers. The array can be declared in MIPS through lw and sll instructions. Each Array has the size and the index for each element stored. Array indexing starts from 0 and the elements can be accessed through the index.

02

Determine the MIPS instruction

Given that, $t1=A and $t2=B. The base address of C is $s1.

To assign the base address of C to $s1, then the lw instruction will be used to load. This will load the element at a 0-byte offset from $s1.

Then for shifting sll instruction is used.

The sequence of MIPS assembly instructions for the

is as follows:

lw $t3,0($s1)

sll $t1,$t3,4

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Most popular questions from this chapter

Question 2.4 [5] For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and \(s7, respectively.

sll \)t0, \(s0, 2 # \)t0 = f * 4

add \(t0, \)s6, \(t0 # \)t0 = &A[f]

sll \(t1, \)s1, 2 # \(t1 = g * 4

add \)t1, \(s7, \)t1 # \(t1 = &B[g]

lw \)s0, 0(\(t0) # f = A[f]

addi \)t2, \(t0, 4

lw \)t0, 0(\(t2)

add \)t0, \(t0, \)s0

sw \(t0, 0(\)t1)

Question: The table below shows 32-bit values of an array stored in memory.

2.6.1 For the memory locations in the table above, write C code to sort the data from lowest to highest, placing the lowest value in the smallest memory location shown in the figure. Assume that the data shown represents the C variable called Array, which is an array of type int, and that the first number in the array shown is the first element in the array. Assume that this particular machine is a byte-addressable machine and a word consists of four bytes.

2.6.2 For the memory locations in the table above, write MIPS code to sort the data from lowest to highest, placing the lowest value in the smallest memory location. Use a minimum number of MIPS instructions. Assume the base address of Array is stored in register $s6.

[5] Consider the following MIPS loop:

LOOP: slt \(t2, \)0, \(t1

beq \)t2, \(0, DONE

subi \)t1, \(t1, 1

addi \)s2, \(s2, 2

j LOOP

DONE:

2.26.1 [5] <§2.7> Assume that the register \)t1 is initialized to the value 10. What is the value in register \(s2 assuming \)s2 is initially zero?

2.26.2 [5] <§2.7> For each of the loops above, write the equivalent C code routine. Assume that the registers \(s1, \)s2, \(t1, and \)t2 are integers A, B, i, and temp, respectively.

2.26.3 [5] <§2.7> For the loops written in MIPS assembly above, assume that the register $t1 is initialized to the value N. How many MIPS instructions are executed?

Question: Provide the type and hexadecimal representation of the following instruction:

sw \(t1, 32(\)t2)

Translate the following MIPS code to C. Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and \(s7, respectively.

addi \)t0, \(s6, 4

add \)t1, \(s6, \)0

sw \(t1, 0(\)t0)

lw \(t0, 0(\)t0)

add \(s0, \)t1, $t0

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