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Question: For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, and i are given and could be considered 32-bit integers as declared in a C program. Use a minimal number of MIPS assembly instructions.

Short Answer

Expert verified

addi f, h, -5

add f, f, g

Step by step solution

01

Determine the MIPS assembly instructions

MIPS is the assembly language that works on the processor as an intermediate between hardware and software. MIPS assembly language works on registers and main memory. All the instructions will have a source register, destination register, and memory location. The sample instructions are add, addi, sub, subi, jr, mul, etc.

02

Determine a minimal number of MIPS assembly instructions for the given C statement.

Given C statement is

MIPS code:

addi f, h, -5

add f, f, g

The above instructions will perform the equivalent operation of the provided C code. The addi instruction will add the immediate value of -5 to the h and save the result in the f. Then the value of g will be added to the f value and the result will be stored in the f register.

For example,

Let g and h be 5 and 10

In MIPS,

addi f,h,-5 //

add f,f,g…..//

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Most popular questions from this chapter

Find the shortest sequence of MIPS instructions that extracts bits 16 down to 11 from register \(t0 and uses the value of this field to replace bits 31 down to 26 in register \)t1 without changing the other 26 bits of register $t1.

Question 2.4 [5] For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and \(s7, respectively.

sll \)t0, \(s0, 2 # \)t0 = f * 4

add \(t0, \)s6, \(t0 # \)t0 = &A[f]

sll \(t1, \)s1, 2 # \(t1 = g * 4

add \)t1, \(s7, \)t1 # \(t1 = &B[g]

lw \)s0, 0(\(t0) # f = A[f]

addi \)t2, \(t0, 4

lw \)t0, 0(\(t2)

add \)t0, \(t0, \)s0

sw \(t0, 0(\)t1)

Question: Assume the following register contents:

  1. For the register values shown above, what is the value of \(t2 for the following sequence of instructions?

sll \)t2,\(t0,44

or \)t2,\(t2,\)t1

  1. For the register values shown above, what is the values of \(t2 for the following sequence of instructions?

sll \)t2,\(t0,4

andi \)t2,\(t2,-1

  1. For the register values shown above, what is the value of \)t2 for the following sequence of instructions?

srl \(t2,\)t0,3

andi \(t2,\)t2, 0xFFEF

Question: Assume that for a given program 70% of the executed instructions are arithmetic, 10% are load/store, and 20% are branch.

2.47.1 [5] <§2.19> Given this instruction mix and the assumption that an

arithmetic instruction requires 2 cycles, a load/store instruction takes 6 cycles, and a branch instruction takes 3 cycles, find the average CPI.

2.47.2 [5] <§2.19> For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

2.47.3 [5] <§2.19> For a 50% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

Question: Consider the following code:

lbu \(t0, 0(\)t1)

sw \(t0, 0(t2)

Assume that the register \)t1 contains the address and the register \(t2 contains the address

. Note the MIPS architecture utilizes big-endian addressing. Assume that the data (in hexadecimal) at the address is . What value is stored at the address pointed to by register \)t2?

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