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[5] Assume for a given processor the CPI of arithmetic instructions is 1, the CPI of load/store instructions is 10, and the CPI of branch instructions is 3.

Assume a program has the following instruction breakdowns: 500 million arithmetic instructions, 300 million load/store instructions, 100 million branch instructions.

2.46.1 [5] <§2.19> Suppose that new, more powerful arithmetic instructions are added to the instruction set. On average, through the use of these more powerful arithmetic instructions, we can reduce the number of arithmetic instructions needed to execute a program by 25%, and the cost of increasing the clock cycle time by only 10%. Is this a good design choice? Why?

2.46.2 [5] <§2.19> Suppose that we find a way to double the performance of arithmetic instructions. What is the overall speedup of our machine? What if we find a way to improve the performance of arithmetic instructions by 10 times?

Short Answer

Expert verified

2.46.1

Increasing the execution time can’t be a good choice.

2.46.2

By assuming, if the performance of arithmetic instructions is doubled then the overall speedup of that machine will be 2.069.

By assuming, if the performance of arithmetic instructions is increased by 10 times then the speedup will be 1.134.

Step by step solution

01

Define the concept.

2.46.1

TheCPI=((CPIarithmeticinstructions×breakdownarithmeticinstructionsbreakdownall)+(CPIloadorstoreinstructions×breakdownloadorstoreinstructionsbreakdownall)+(CPIbranchinstructions×breakdownbranchinstructionsbreakdownall))

the execution time = the CPI x f x the sum of all these breakdown

2.46.2

The CPI of the arithmetic instructions is 1.

By assuming, the performance of arithmetic instructions is doubled.

So, ( 1×0.5) = 0.5

Speed up =CPIatthestartingCPIafterincreasingtheperformanceofarithmeticinstructions

02

Determine the calculation.

Given,

The CPI of the arithmetic instructions is 1.

The CPI of the load or store instructions is 10.

The CPI of the branch instructions is 13.

The breakdown of the arithmetic instructions is 500 million.

The breakdown of the load or store instructions is 300 million.

The breakdown of the branch instructions is 100 million.

The sum of all these breakdown = (500+300+100) = 900 million.

At the start, The CPI

=10×300900+1×500900+3×100900=103+59+13=389=4.22

Let’s assume, to execute a program the number of arithmetic instructions can be reduced by 25%.

Now, the total arithmetic = 0.75 x 500 =375

At the start, the execution time =389×f×900=3800f

The sum of these breakdown = (375+300+100) = 775 million.

Now, the CPI =10×300775+1×375775+3×100775=3675775

And also by assuming that the cost of increasing the clock cycle time by only 10%

Now, the executive time=3675775×f×1+0.1×775=3675775×f×1.1×775=4042.5f

Hence the current execution time > the previous execution time.

Increasing the execution time can’t be a good choice.

2.46.2

By assuming, the performance of arithmetic instructions is doubled.

At the start, the CPI is 4.22.

Now, the CPI =10×39+0.5×59+3×19=3.944

Now, the speed up=4.223.944=1.069

By assuming, the performance of arithmetic instructions is increased by 10 times.

Now, the CPI=10×39+0.5×19+3×19=30+0.5+39=33.59=3.72Now,thespeedup=4.223.72=1.134

Overall speedup = 1.134

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Most popular questions from this chapter

Question: [5] Consider the following MIPS loop:

LOOP: slt \(t2, \)0, \(t1

beq \)t2, \(0, DONE

subi \)t1, \(t1, 1

addi \)s2, \(s2, 2

j LOOP

DONE:

2.26.1 [5] <§2.7> Assume that the register \)t1 is initialized to the value 10. What is the value in register \(s2 assuming \)s2 is initially zero?

2.26.2 [5] <§2.7> For each of the loops above, write the equivalent C code routine. Assume that the registers \(s1, \)s2, \(t1, and \)t2 are integers A, B, i, and temp, respectively.

2.26.3 [5] <§2.7> For the loops written in MIPS assembly above, assume that the register $t1 is initialized to the value N. How many MIPS instructions are executed?

Question: Assume that for a given program 70% of the executed instructions are arithmetic, 10% are load/store, and 20% are branch.

2.47.1 [5] <§2.19> Given this instruction mix and the assumption that an

arithmetic instruction requires 2 cycles, a load/store instruction takes 6 cycles, and a branch instruction takes 3 cycles, find the average CPI.

2.47.2 [5] <§2.19> For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

2.47.3 [5] <§2.19> For a 50% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields: op=0, rs=3, rt=2, rd=3, shamt=0, funct=34

For each MIPS instruction, show the value of the opcode(OP), source register(RS), and target register(RT) fields. For the I-type instructions, show the value of the immediate field, and for the R-type instructions, show the value of the destination register(RD) field.

addi \(t0,\)s6,4

add \(t1.\)s6,\(0

sw \)t1, 0(\(t0)

lw \)t0,0(\(t0)

add \)s0,\(t1,\)t0

Question [5] <§2.7> Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, i, and j are in registers \(s0, \)s1, \(t0, and \)t1, respectively. Also, assume that register $s2 holds the base address of the array D.

for(i=0; i<a; i++)

for(j=0; j<b; j++)

D[4*j] = i + j;

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