Warning: foreach() argument must be of type array|object, bool given in /var/www/html/web/app/themes/studypress-core-theme/template-parts/header/mobile-offcanvas.php on line 20

If the current value of the PC is 0x00000600, can you use a single jump instruction to get to the PC address as shown in Exercise 2.39?

Short Answer

Expert verified

No, since the range is 0xFFFFE604 ~ 0X00020600

Step by step solution

01

Determine the MIPS jump instruction

The MIPS assembly language has the j instruction to perform the jump. The address of the target will be reached through jump only if the target address lies within the jump range.

For example:

j 3500

The above instruction will jump to the target address.

02

Determine whether the single jump instruction will be enough to get to the PC address.

The given value of PC is 0x00000600.

For the jump instruction the address range can be calculated as follows:

Let us consider the register values from the exercise 2.39 as given in the question.

Range:

PC+4+0×1FFFC=0×00000600+4+0×1FFFC=0×00020600

The value of PC is added with the base register value and the value of register from exercise 2.39 is added.

PC+4-0×02000000=0×00000600+4-0×02000000=0×FFFE0604

The above is the range of the jump instruction.

So, No single jump instruction can be used, because the range of the jump is 0×FFFFE604~0×00020600

One App. One Place for Learning.

All the tools & learning materials you need for study success - in one app.

Get started for free

Most popular questions from this chapter

Consider the following code:

lbu \(t0, 0(\)t1)

sw \(t0, 0(t2)

Assume that the register \)t1 contains the address 0×10000000and the register \(t2 contains the address 0×10000010. Note the MIPS architecture utilizes big-endian addressing. Assume that the data (in hexadecimal) at the address role="math" localid="1650309285539" 0×10000000is 0×11223344 . What value is stored at the address pointed to by register \)t2?

Find the shortest sequence of MIPS instructions that extracts bits 16 down to 11 from register \(t0 and uses the value of this field to replace bits 31 down to 26 in register \)t1 without changing the other 26 bits of register $t1.

Question: Provide the type and hexadecimal representation of the following instruction:

sw \(t1, 32(\)t2)

Question: Repeat Exercise 2.43, but this time use ll/sc to perform an atomic update of the shvar variable directly, without using lock() and unlock(). Note that in this problem there is no variable lk.

Question: [5] Consider the following MIPS loop:

LOOP: slt \(t2, \)0, \(t1

beq \)t2, \(0, DONE

subi \)t1, \(t1, 1

addi \)s2, \(s2, 2

j LOOP

DONE:

2.26.1 [5] <§2.7> Assume that the register \)t1 is initialized to the value 10. What is the value in register \(s2 assuming \)s2 is initially zero?

2.26.2 [5] <§2.7> For each of the loops above, write the equivalent C code routine. Assume that the registers \(s1, \)s2, \(t1, and \)t2 are integers A, B, i, and temp, respectively.

2.26.3 [5] <§2.7> For the loops written in MIPS assembly above, assume that the register $t1 is initialized to the value N. How many MIPS instructions are executed?

See all solutions

Recommended explanations on Computer Science Textbooks

View all explanations

What do you think about this solution?

We value your feedback to improve our textbook solutions.

Study anywhere. Anytime. Across all devices.

Sign-up for free