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Rewrite the loop from Exercise 2.29 to reduce the number of MIPS instructions executed

Short Answer

Expert verified

The reduce number of Mips instructions are:

addi $t1, $s0, 400

LOOP: lw $s1, 0($t1)

add $s2, $s2, $s1

addi $t1, $t1, -4

bne $t1, $s0 LOOP

Step by step solution

01

MIPS instructions used in Exercise 2.29

addi: It is short for add immediate

lw: It is short for load word

add: It is an arithmetic operation used to add

slti: It is short for set on less than or equal

bne: it is short for the branch on not equal it test if registers are not equal

02

Given MIPS instruction

addi $t1, $0, $0

LOOP: lw $s1, 0($s0)

add $t2, $s0

addi $s0. $s0, 4

addi $t1, $t1, 1

slti $t2, $t1, 100

bne $t2, $s0, LOOP

03

Rewrite the loop to Minimize the number of MIPS instruction

Here, we used variable only for loop control

Now, reduce the number of MIPS instruction

addi $t1, $s0, 400 # add a constant number

LOOP: lw $s1, 0($t1) # load word

add $s2, $s2, $s1 # add first element

addi $s2, $s2, $s1 # add immediate and immediate means a constant no.

bne $t1, $s0, LOOP #Loop until the pointer reaches limit

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Most popular questions from this chapter

Translate the following MIPS code to C. Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and \(s7, respectively.

addi\)t0, \(s6, 4

add \)t1, \(s6, \)0

sw \(t1, 0(\)t0)

lw \(t0, 0(\)t0)

add \(s0, \)t1, $t0

Question: The following instruction is not included in the MIPS instruction set:

rpt $t2, loop # if(R[rs]>0) R[rs]=R[rs]−1, PC=PC+4+BranchAddr

2.25.1 [5] <§2.7> If this instruction were to be implemented in the MIPS

instruction set, what is the most appropriate instruction format?

2.25.2 [5] <§2.7> What is the shortest sequence of MIPS instructions that

performs the same operation?

Question 2.4 [5] For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and \(s7, respectively.

sll \)t0, \(s0, 2 # \)t0 = f * 4

add \(t0, \)s6, \(t0 # \)t0 = &A[f]

sll \(t1, \)s1, 2 # \(t1 = g * 4

add \)t1, \(s7, \)t1 # \(t1 = &B[g]

lw \)s0, 0(\(t0) # f = A[f]

addi \)t2, \(t0, 4

lw \)t0, 0(\(t2)

add \)t0, \(t0, \)s0

sw \(t0, 0(\)t1)

Write the MIPS assembly code that creates the 32-bit constant 0010 0000 0000 0001 0100 1001 0010 0100 and stores that value to register $t1.

For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and $s7, respectively.

B[8]=A[i-j]

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