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For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and $s7, respectively.

B8=Ai-j;

Short Answer

Expert verified

MIPS assembly code is

sub $t1, $s3, $s4

sll $t2, $t1, 2

add $t3, $s6, $t2

lw $t1, 0(t3)

sw $t1, 32($s7)

Step by step solution

01

Define MIPS assembly code

MIPS stands for Microprocessor without interlocked pipeline. To write MIPS assembly code we should know about Registers and instructions format each MIPS instruction is of 32 bits.

02

Convert C code into MIPS assembly code

C code:B8=Ai-j;

Now compiled MIPS code

MIPS code

comment

sub $t1, $s3, $s4

$t1 = (i - j), i is assigned to register $s3 and j is assigned to register $s4

sll $t2, $t1, 2

shift left by a constant number of bits

add $t3, $s6, $t2

$t3 = the address of A [i - j]

lw $t1, 0(t3)

$t1 = A[i - j] copy from memory to register

sw $t1, 32($s7)

B[8] = A[i - j] copy from register to memory

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Most popular questions from this chapter

[5] <§2.7> Suppose the program counter (PC) is set to 0x2000 0000. Is it possible to use the jump (j) MIPS assembly instruction to set the PC to the address as 0x4000 0000? Is it possible to use the branch-on-equal (beq) MIPS assembly instruction to set the PC to this same address?

Question: For each MIPS instruction, show the value of the opcode(OP), source register(RS), and target register(RT) fields. For the I-type instructions, show the value of the immediate field, and for the R-type instructions, show the value of the destination register(RD) field.

addi \(t0,\)s6,4

add \(t1.\)s6,\(0

sw \)t1, 0(\(t0)

lw \)t0,0(\(t0)

add \)s0,\(t1,\)t0

Assume that for a given program 70% of the executed instructions are arithmetic, 10% are load/store, and 20% are branch.

2.47.1 [5] <§2.19> Given this instruction mix and the assumption that an

arithmetic instruction requires 2 cycles, a load/store instruction takes 6 cycles, and a branch instruction takes 3 cycles, find the average CPI.

2.47.2 [5] <§2.19> For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

2.47.3 [5] <§2.19> For a 50% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

Question: Using your code from Exercise 2.43 as an example, explain what happens when two processors begin to execute this critical section at the same time, assuming that each processor executed exactly one instruction per cycle.

If the current value of the PC is 0x00000600, can you use a single jump instruction to get to the PC address as shown in Exercise 2.39?

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