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[5] <§2.7> Suppose the program counter (PC) is set to 0x2000 0000. Is it possible to use the jump (j) MIPS assembly instruction to set the PC to the address as 0x4000 0000? Is it possible to use the branch-on-equal (beq) MIPS assembly instruction to set the PC to this same address?

Short Answer

Expert verified

No, it is not possible to set the pc address as 0x4000 0000 by using the MIPS assembly instruction “jump(j)” from the PC address 0x2000 0000.

No, it is not possible to set the PC to this same address by using the branch-on-equal (beq) MIPS assembly instruction.

Step by step solution

01

Define the concept of “jump(j)” and “branch-on-equal(beq)”.

The “jump(j)” is the MIPS assembly instructions. This instruction is used for transferring the sequence of the program to the specified memory address. The purpose of using this MIPS assembly instruction -“j 2400”is to jump to the specified memory address “2400”.

The “branch-on-equal (beq)” is a decision-making instruction in MIPS assembly language. The purpose of using this MIPS assembly instruction “beq reg1, reg2 Label” is going to the statement “Label” if the value of “reg1” is equal to the “reg2”.

02

Determine the possibility of the mentioned condition.

The “jump(j)” can able to transfer the program sequence to the full 32-bit address. But by using a single instruction, it is not possible to transfer the program sequence to the specified address where the address is greater than 28 bits.

The “branch-on-equal(beq)” is I type instruction in MIPS assembly language. Therefore, it is not possible to use the branch-on-equal (beq) MIPS assembly instruction to set the PC to this same address as the specified memory address is greater than the 16 bits.

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Most popular questions from this chapter

[5] <§2.7> Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, i, and j are in registers \(s0, \)s1, \(t0, and \)t1, respectively. Also, assume that register $s2 holds the base address of the array D.

for(i=0; i<a; i++)

for(j=0; j<b; j++)

D[4*j] = i + j;

Question: Assume that for a given program 70% of the executed instructions are arithmetic, 10% are load/store, and 20% are branch.

2.47.1 [5] <§2.19> Given this instruction mix and the assumption that an

arithmetic instruction requires 2 cycles, a load/store instruction takes 6 cycles, and a branch instruction takes 3 cycles, find the average CPI.

2.47.2 [5] <§2.19> For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

2.47.3 [5] <§2.19> For a 50% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?

Question: Write the MIPS assembly code to implement the following C code:

lock(lk);

shvar=max(shvar.x);

unlock(lk);

Assume that the address of the lk variable is in \(a0, the address of the shvar variable is in \)a1, and the value of variable x is in $a2. Your critical section should not contain any function calls. Use ll/sc instructions to implement the lock() operation and the unlock() operation is simply an ordinary store instruction.

For the MIPS assembly instructions in Exercise 2.4, rewrite the assembly code to minimize the number if MIPS instructions (if possible) needed to carry out the same function.

Write the MIPS assembly code that creates the 32-bit constant 0010 0000 0000 0001 0100 1001 0010 0100 and stores that value to register $t1.

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