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Provide a minimal set of MIPS instructions that may be used to implement the following pseudo instruction:

not \(t1,\)t2 // bit-wise invert

Short Answer

Expert verified

The MIPS instructions that are used to implement the given pseudo instruction is as follows:

nor $t1,$t2,$t2

Step by step solution

01

Define MIPS logical instructions.

MIPS logical instructions are sll, srl, and, andi, or, ori, and nor. The sll and srl are the shift instructions that make the left and a right shift in the bits of the registers. The and, or instructions perform logical AND, OR operations between the data in the registers. To perform logical operations on immediate values andi, ori instructions are used. Instead of NOT, nor is used in MIPS assembly language.

02

Determine the MIPS instruction

In MIPS, instead of NOT, nor is used to perform the NOT operation. Instruction nor will provide the inverted bit of the operand involved.

Pseudo instruction:

not $t1,$t2

For example, let us consider the value of $t2 to be 10100, then the NOT operation will be performed. After the NOT operation, the bits of $t2 will be inverted bit by bit and the value of $t1 will be 01011.

MIPS instruction:

nor $t1,$t2,$t2

The above instruction will perform the NOT OR, which results in NOT operation.

For example, let us consider the value of $t2 to be 10101, then the value of $t2 will perform OR operation with 0. Then the value of $t2 will 10101. Now the NOT will be performed on the value of $t2 and the result 01010 will be stored in the $t1 register.

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Most popular questions from this chapter

Question: For the following MIPS assembly instructions above, what is a corresponding C statement?

add f, g, h

add f, i, f

Question: Can we use the tail-call optimization in this function? If no, explain why not. If yes, what is the difference in the number of executed instructions in f with and without the optimization?

Question: Consider the following code:

lbu \(t0, 0(\)t1)

sw \(t0, 0(t2)

Assume that the register \)t1 contains the address and the register \(t2 contains the address

. Note the MIPS architecture utilizes big-endian addressing. Assume that the data (in hexadecimal) at the address is . What value is stored at the address pointed to by register \)t2?

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2.6.1 For the memory locations in the table above, write C code to sort the data from lowest to highest, placing the lowest value in the smallest memory location shown in the figure. Assume that the data shown represents the C variable called Array, which is an array of type int, and that the first number in the array shown is the first element in the array. Assume that this particular machine is a byte-addressable machine and a word consists of four bytes.

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Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields:

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