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Assume the following register contents:

\(t0=0×AAAAAAAA, \)t1=0×12345678

1. For the register values shown above, what is the value of \(t2 for the following sequence of instructions?

sll \)t2,\(t0,44

or \)t2,\(t2,\)t1

2. For the register values shown above, what is the values of \(t2 for the following sequence of instructions?

sll \)t2,\(t0,4

andi \)t2,\(t2,-1

3. For the register values shown above, what is the value of \)t2 for the following sequence of instructions?

srl \(t2,\)t0,3

andi \(t2,\)t2, 0xFFEF

Short Answer

Expert verified

Value of $t2 after the execution of given sequence of instructions:

1.0×BABEFEF82.0×AAAAAAA03.0×00005545

Step by step solution

01

Define MIPS instructions.

MIPS instructions perform arithmetic operations on registers. MIPS instructions also transfer data between memory and registers. The MIPS assembly language use 32 registers, namely $s0-$s7 and $t0-$t9, $zero, $a0-$a3 etc.

MIPS uses byte addresses, that allow memory to hold data structures, arrays, and registers.

02

Determine the value of $t2. 

1. The given register contents are,

Instruction:

sll $t2,$t0,44

or $t2,$t2,$t1

The instruction sll will make the logical left shift on $t0, but shift 44 is not negligible because we use only 32 registers, in this case, shift 30 and 14.The value of $t2 is 0xAAAAAA0

Then, the result is stored in $t2.

Now, the value of $t2 and $t1 will perform the logical operation OR.

The values AAAAAAA0 OR 12345678 will be performed.

Then the result $t2= 0xBABEFEF8

03

Determine the value of $t2.

2. The given register contents are,

Instruction:

sll $t2,$t0,4

andi $t2,$t2,-1

The instruction srl will make the logical right shift on $t0.Then, the value of $t2 is 0xAAAAAAA0

Then, the result is stored in $t2.

Now, the value of $t2 will perform the logical operation AND with immediate -1.

The values AAAAAAA0 AND -1 will be performed.

Then the result $t2=0xAAAAAAA0

04

Determine the value of $t2.

3. The given register contents are,

Instruction:

srl $t2,$t0,3

andi $t2,$t2,0xFFEF

The instruction srl will make the logical right shift on $t0.Then ,The value of $t2 is 0x15555555

Then, the result is stored in $t2.

Now, the value of $t2 will perform the logical operation AND with immediate 0xFFEF

The values 0AAAAAAA AND 0xFFEF will be performed.

Then, the result $t2= 0x00005545

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Most popular questions from this chapter

Assume that registers \(s0 and \)s1 hold the values 0x80000000 and 0xD0000000, respectively.

1. What is the value of \(t0 for the following assembly code?

add \)t0,\(s0,\)s1

2. Is the result in \(t0 the desired result, or has there been an overflow?

3. For the contents of registers \)s0 and \(s1 as specified above, what is the value of \)t0 for the following assembly code?

sub \(t0,\)s0,\(s1

4. Is the result in \)t0 the desired result, or has there been an overflow?

5. For the contents of registers \(s0 and \)s1 as specified above, What is the value of \(t0 for the following assembly code?

add \)t0,\(s0,\)s1

add \(t0,\)t0,\(s0

6. Is the result in \)t0 the desired result, or has there been an overflow?

Question: [5] Consider the following MIPS loop:

LOOP: slt \(t2, \)0, \(t1

beq \)t2, \(0, DONE

subi \)t1, \(t1, 1

addi \)s2, \(s2, 2

j LOOP

DONE:

2.26.1 [5] <§2.7> Assume that the register \)t1 is initialized to the value 10. What is the value in register \(s2 assuming \)s2 is initially zero?

2.26.2 [5] <§2.7> For each of the loops above, write the equivalent C code routine. Assume that the registers \(s1, \)s2, \(t1, and \)t2 are integers A, B, i, and temp, respectively.

2.26.3 [5] <§2.7> For the loops written in MIPS assembly above, assume that the register $t1 is initialized to the value N. How many MIPS instructions are executed?

Question: For the following MIPS assembly instructions above, what is a corresponding C statement?

add f, g, h

add f, i, f

[5] Assume for a given processor the CPI of arithmetic instructions is 1, the CPI of load/store instructions is 10, and the CPI of branch instructions is 3.

Assume a program has the following instruction breakdowns: 500 million arithmetic instructions, 300 million load/store instructions, 100 million branch instructions.

2.46.1 [5] <§2.19> Suppose that new, more powerful arithmetic instructions are added to the instruction set. On average, through the use of these more powerful arithmetic instructions, we can reduce the number of arithmetic instructions needed to execute a program by 25%, and the cost of increasing the clock cycle time by only 10%. Is this a good design choice? Why?

2.46.2 [5] <§2.19> Suppose that we find a way to double the performance of arithmetic instructions. What is the overall speedup of our machine? What if we find a way to improve the performance of arithmetic instructions by 10 times?

If the current value of the PC is 0x1FFFf000, can you use a single jump instruction to get to the PC address as shown in Exercise 2.39?

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