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Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields: op=0, rs=3, rt=2, rd=3, shamt=0, funct=34

Short Answer

Expert verified

This is a I type instruction

MIPS: lw $2, 4[$1]

Binary: 100011 00001 00010 0000000000000100

Step by step solution

01

Determine op=0:Determine rs=3, rt=2, rd=3Determine shamt=0Determine Funct=34

op=0, rs=3, rt=2, rd=3, shamt=0, funct=34

this is R-type instruction

opcode :
The opcode is the machine code representation of the instruction mnemonic. Several related instructions can have the same opcode. The opcode field is 6 bits long (bit 26 to bit 31).

rs, rt, rd:

The numeric representations of the source registers and the destination register. These numbers correspond to the $X representation of a register, such as $0 or $31. Each of these fields is 5 bits long. (25 to 21, 20 to 16, and 15 to 11, respectively). Interestingly, rather than rs and rt being named r1 and r2 (for source register 1 and 2), the registers were named "rs" and "rt" because t comes after s in the alphabet. This was most likely done to reduce numerical confusion.

Shift (shamt):
Used with the shift and rotate instructions, this is the amount by which the source operand rs is rotated/shifted. This field is 5 bits long (6 to 10).

Funct:

For instructions that share an opcode, the funct parameter contains the necessary control codes to differentiate the different instructions. 6 bits long (0 to 5).
Example: Opcode 0x00 accesses the ALU, and the funct selects which ALU function to use

02

Converting MIPS fields to Assembly language

op=0 ---------> represents Add function. As several related instructions can have the same opcode we will consider the function also.

Funct =34 ------> converting decimal 34 to hexadecimal 0x22 which represent "sub" function.

ultimately ,the function which has opcode '0' and function '0x22' is "sub" function.

finally, the assembly level instruction is

sub $3, $3, $2

(rd rs rt)

03

conversion to binary format

R Format:

Converting an R mnemonic into the equivalent binary machine code is performed in the following way:


opcode

rs

rt

rd

shift

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

opcode of sub is '0' and six bit long - 000000
rd,rs,rt,shift are five bit long so,
rd = $3 = 00011
rs = $3 = 00011
rt = $2 = 00010
shift = 0 = 00000
function is also six bit long ,funct = 34 = 100010

Now, put all binary numbers in a single line in the order mentioned above in the table that is your binary conversion of MIPS fields given;

000000 00011 00010 00011 00000 100010 ------> 621822(hexadecimal value)

op=0x23, rs=1, rt=2, const=0x4

op=0x23 represent " load word" i.e., lw
rs=1 represents "$1"
rt=2 represents "$2"
const=0x4

This is a I type instruction

MIPS: lw $2, 4[$1]

Binary: 100011 00001 00010 0000000000000100

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Most popular questions from this chapter

Question: For each MIPS instruction, show the value of the opcode(OP), source register(RS), and target register(RT) fields. For the I-type instructions, show the value of the immediate field, and for the R-type instructions, show the value of the destination register(RD) field.

addi \(t0,\)s6,4

add \(t1.\)s6,\(0

sw \)t1, 0(\(t0)

lw \)t0,0(\(t0)

add \)s0,\(t1,\)t0

Question: Provide the type and assembly language instruction for the following binary value:

Question: Assume the following register contents:

  1. For the register values shown above, what is the value of \(t2 for the following sequence of instructions?

sll \)t2,\(t0,44

or \)t2,\(t2,\)t1

  1. For the register values shown above, what is the values of \(t2 for the following sequence of instructions?

sll \)t2,\(t0,4

andi \)t2,\(t2,-1

  1. For the register values shown above, what is the value of \)t2 for the following sequence of instructions?

srl \(t2,\)t0,3

andi \(t2,\)t2, 0xFFEF

Assume that registers \(s0 and \)s1 hold the values 0x80000000 and 0xD0000000, respectively.

1. What is the value of \(t0 for the following assembly code?

add \)t0,\(s0,\)s1

2. Is the result in \(t0 the desired result, or has there been an overflow?

3. For the contents of registers \)s0 and \(s1 as specified above, what is the value of \)t0 for the following assembly code?

sub \(t0,\)s0,\(s1

4. Is the result in \)t0 the desired result, or has there been an overflow?

5. For the contents of registers \(s0 and \)s1 as specified above, What is the value of \(t0 for the following assembly code?

add \)t0,\(s0,\)s1

add \(t0,\)t0,\(s0

6. Is the result in \)t0 the desired result, or has there been an overflow?

Assume the following register contents:

\(t0=0ร—AAAAAAAA, \)t1=0ร—12345678

1. For the register values shown above, what is the value of \(t2 for the following sequence of instructions?

sll \)t2,\(t0,44

or \)t2,\(t2,\)t1

2. For the register values shown above, what is the values of \(t2 for the following sequence of instructions?

sll \)t2,\(t0,4

andi \)t2,\(t2,-1

3. For the register values shown above, what is the value of \)t2 for the following sequence of instructions?

srl \(t2,\)t0,3

andi \(t2,\)t2, 0xFFEF

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