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Translate the following MIPS code to C. Assume that the variables f, g, h, i, and j are assigned to registers \(s0, \)s1, \(s2, \)s3, and \(s4, respectively. Assume that the base address of the arrays A and B are in registers \)s6 and \(s7, respectively.

addi \)t0, \(s6, 4

add \)t1, \(s6, \)0

sw \(t1, 0(\)t0)

lw \(t0, 0(\)t0)

add \(s0, \)t1, $t0

Short Answer

Expert verified

The C code:

A [1] = A[0];

f = & A[0] + A[1];

Step by step solution

01

Define MIPS assembly code

MIPS stands for Microprocessor without interlocked pipeline. To write MIPS assembly code we should know about Registers and instructions format each MIPS instruction is of 32 bits

02

Convert addi  $t0,   $s6,  4 MIPS code to C

addi $t0,$s6,4

$t0=$s6+4$t0=&A[1]

03

Convert add  $t1, $s6, $0 MIPS code to C

add$t1,$s6,$0$t1=$s6+$0$t1=$s6$t1=&A[0]

04

Convert sw $t1, 0($t0) MIPS code to C

sw$t1,0($t0)Memory[$t0+0]=$t1Memory[&A0]=$t1

A[0] will have the address of A[1]

05

Convert lw $t0, 0($t0) MIPS code to C

lw$t0,0($t0)$t0=Memory[$t0+0]$=Memory[$t0]=Memory[&A[1]]

06

Convert add  $s0, $t1, $t0 MIPS code to C

add$s0,$t1,$t0

$s0=$t1+$t0=&A[0]+A[1]f=&A[0]+A[1]

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Most popular questions from this chapter

Question: For each MIPS instruction, show the value of the opcode(OP), source register(RS), and target register(RT) fields. For the I-type instructions, show the value of the immediate field, and for the R-type instructions, show the value of the destination register(RD) field.

addi \(t0,\)s6,4

add \(t1.\)s6,\(0

sw \)t1, 0(\(t0)

lw \)t0,0(\(t0)

add \)s0,\(t1,\)t0

Question: Using your code from Exercise 2.43 as an example, explain what happens when two processors begin to execute this critical section at the same time, assuming that each processor executed exactly one instruction per cycle.

Provide a minimal set of MIPS instructions that may be used to implement the following pseudo instruction:

not \(t1,\)t2 // bit-wise invert

Question: [5] Consider the following MIPS loop:

LOOP: slt \(t2, \)0, \(t1

beq \)t2, \(0, DONE

subi \)t1, \(t1, 1

addi \)s2, \(s2, 2

j LOOP

DONE:

2.26.1 [5] <ยง2.7> Assume that the register \)t1 is initialized to the value 10. What is the value in register \(s2 assuming \)s2 is initially zero?

2.26.2 [5] <ยง2.7> For each of the loops above, write the equivalent C code routine. Assume that the registers \(s1, \)s2, \(t1, and \)t2 are integers A, B, i, and temp, respectively.

2.26.3 [5] <ยง2.7> For the loops written in MIPS assembly above, assume that the register $t1 is initialized to the value N. How many MIPS instructions are executed?

Provide the type and assembly language instruction for the following binary value: 0000 0010 0001 0000 1000 0000 0010 0000two.

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