Chapter 1: Q7E (page 2)
Construct the truth table for a four-input odd-parity function (see page B-65 for a description of parity).
The parity bit is 1 for 0000, 0011, 0101, 0110, 1001, 1010, 1100, 1111 and the parity bit is 0 for 0001, 0010, 0100, 0111, 1000, 1011, 1101, 1110.
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Implement the four-input odd-parity function with AND and OR gates using bubbled inputs and outputs.
What is the function implemented by the following Verilog modules:
Module FUNC1 (I0, I1, S, out):
input I0, I1;
input S;
output out;
out = S? I1: I0;
endmodule
module FUNC2 (out, ctl, clk,reset);
output [7:0] out;
input ctl, clk, reset;
reg [7:0] out;
always @(posedge clk)
if (reset) begin
out <= 8’b0;
end
else if (ctl) begin
out <= out+1;
end
else begin
out <= out-1;
end
endmodule
Now we wish to add the instructionaddi(add immediate). Add any necessary changes to the datapath and to the control signals. How many product terms are required in a PLA that implements the control for the single-cycle datapath foraddiu?
B.27 [15] <§B.6> Write the equations for the carry-lookahead logic for a 64- bit adder using the new notation from Exercise B.26 and using 16-bit adders as building blocks. Include a drawing similar to Figure B.6.3 in your solution.
Prove that a two-input multiplexor is also universal by showing how to build the NAND (or NOR) gate using a multiplexor
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