Question

Quite often, you would expect that given a timing diagram containing a description of changes that take place on a data input D and a clock input C (as in Figures B.8.3 and B.8.6 on pages B-52 and B-54, respectively), there would be differences between the output waveforms (Q) for a D latch and a D flip-flop. In a sentence or two, describe the circumstances (e.g., the nature of the inputs) for which there would not be any difference between the two output waveforms.

Short answer

The output of the D latch and D flip-flop is the same there is no change in the input signal whenever the clock is high and transitions from high-to-low.

Step-by-step solution

Definition of the D latch

D latch is level sensitive. The D latch matches the input if the clock is high. When the clock is low, the latch holds the value. Consider the following figure,

On the first low-to-high transition of the clock, the output is the same as the input. And it matches the input till the clock is high. When the clock transits from high-to-low, the output of the latch holds the last value. On the second low-to-high transition, the output matches the input.

Definition of D flip-flop

D flip-flop is edge triggered. When the clock goes from high-to-low, the output of the D flip-flop matches the input till the next high-to-low transition. Consider the following figure,

On every high-to-low transition, the output of the D flip-flop matches the input till the next high-to-low transition.

D latch and D flip-flop with the same output

D-latch changes its output when the clock is high and D flip-flop changes its output while the high-to-low transition of the clock. If the input stays the same while the clock the high and the transition from high-to-low, the output of the D latch and D flip-flop will be the same.