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Perhaps the most likely case of adding many numbers at once in a computer would be when trying to multiply more quickly by using any adders to add many numbers in a single clock cycle. Compared to the multiply algorithm in Chapter 3, a carry save scheme with many adders could multiply more than 10 times faster. This exercise estimates the cost and speed of a combinational multiplier to multiply two positive 16-bit numbers. Assume that you have 16 intermediate terms M15, M14, …, M0, called partial products, that contain the multiplicand ANDed with multiplier bits m15, m14, …, m0. The idea is to use carry save adders to reduce the noperands into 2n/3 in parallel groups of three, and do this repeatedly until you get two large numbers to add together with a traditional adder.

First, show the block organization of the 16-bit carry save adders to add these 16 terms, as shown on the right in Figure B.14.1. Then calculate the delays to add these 16 numbers. Compare this time to the iterative multiplication scheme in Chapter 3 but only assume 16 iterations using a 16-bit adder that has full carry lookahead whose speed was calculated in Exercise B.29.

Short Answer

Expert verified

Block organization of the 16-bit carry save address to add 16 terms is as follows:

Time consumed=296T

Speed up=8.22

Step by step solution

01

Determine the faster addition

The faster addition can be performed by finding the carry in the higher order bits . The faster method of finding carry will speedup the addition. “Infinite” Hardware can be used to find the fast carry. But this increases the expenses that spent in hardware units. Carry-lookahead adder is capable of finding the fast carry with speed improvements.

02

Determine the block organization and speed up.

Given:

Combinational multiplier to multiply two 16-bit numbers is introduced.

Assume that there are 16 intermediate terms M15 to M0, called partial products that contain the multiplican ANDed with multiplier bits m15 to m0.

This idea will be used to carry save adders to reduce the n operands to 2n/3 in parallel groups of three.

This will generate two larger numbers that will be added in the traditional adder.

The block diagram , that shows the 16 bit carry save adders to add 16 terms is shown below:

From, the block orgranization, it is depicted that the partial products are grouped in each level. Each group will be processed in parallel with four carry save adders in the level 1.

Likewise , sum of the larger numbers will be found in the level 7.

We know that , there are 7 levels involved in the calculation of the sum of 16 partial products.

From, level 1 to 6 each level will consume 2T time to perform sum.In level 7 carry look ahead adder will consume around 8T time.

The total time consumed will be:

2T×6+24T=36T

If the multiplication is carried out using traditional look ahead adder, Then the time consumed would be:

For

M0:16bits=8TM1:17bits=12TM2:18bits=12TM3:19bits=12TM4:20bits=12TM5:21bits=16TM6:22bits=16TM7:23bits=16TM8:24bits=16TM9:25bits=20TM10:26bits=20TM11:27bits=20TM12:28bits=20TM13:29bits=24TM14:30bits=24TM15:31bits=24TM16:32bits=24T

Above is the calculation for time consumed for each partial product on the traditional look ahead adder.

Total time consumed will be:

T=8T+12T×4+16T×4+20T×4+24T×4=8T+48T+64T+80T+96T=296T

Speed up is the ratio between the carry save adder orgranization and the traditional look ahead adder.

Speedup=29632=8.22

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Most popular questions from this chapter

Prove that the NAND gate is universal by showing how to build the AND, OR, and NOT functions using a two-input NAND gate.

Implement the four-input odd-parity function with AND and OR gates using bubbled inputs and outputs.

2 Section 1.10 cites as a pitfall the utilization of a subset of the performance equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4 GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3 GHz, an average CPI of 0.75, and requires the execution of 1.0E9 instructions.

1.12.1 [5] <§§1.6, 1.10> One usual fallacy is to consider the computer with the largest clock rate as having the largest performance. Check if this is true for P1 and P2.

1.12.2 [10] <§§1.6, 1.10> Another fallacy is to consider that the processor executing the largest number of instructions will need a larger CPU time. Considering that processor P1 is executing a sequence of 1.0E9 instructions and that the CPI of processors P1 and P2 do not change, determine the number of instructions that P2 can execute in the same time that P1 needs to execute 1.0E9 instructions.

1.12.3 [10] <§§1.6, 1.10> A common fallacy is to use MIPS (millions of

instructions per second) to compare the performance of two different processors, and consider that the processor with the largest MIPS has the largest performance.

Check if this is true for P1 and P2.

1.12.4 [10] <§1.10> Another common performance figure is MFLOPS (millions of floating-point operations per second), defined as

MFLOPS = No. FP operations / (execution time × 1E6)

but this figure has the same problems as MIPS. Assume that 40% of the instructions executed on both P1 and P2 are floating-point instructions. Find the MFLOPS figures for the programs

B.30 [15] <§B.6> This exercise is similar to Exercises B.28 and B.29, but this time calculate the relative speeds of a 64-bit adder using ripple carry only, ripple carry of 4-bit groups that use carry lookahead, ripple carry of 16-bit groups that use carry lookahead, and the carry-lookahead scheme from Exercise B.27.

Quite often, you would expect that given a timing diagram containing a description of changes that take place on a data input D and a clock input C (as in Figures B.8.3 and B.8.6 on pages B-52 and B-54, respectively), there would be differences between the output waveforms (Q) for a D latch and a D flip-flop. In a sentence or two, describe the circumstances (e.g., the nature of the inputs) for which there would not be any difference between the two output waveforms.

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