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B.31 [10] <§B.6> Instead of thinking of an adder as a device that adds: two numbers and then links the carries together, we can think of the adder as a hardware device that can add three inputs together (ai, bi, ci) and produce two outputs (s, ci + 1). When adding two numbers together, there is little we can do with this observation. When we are adding more than two operands, it is possible to reduce the cost of the carry. The idea is to form two independent sums, called S (sum bits) and C (carry bits). At the end of the process, we need to add C and S together using a normal adder. This technique of delaying carry propagation until the end of a sum of numbers is called carry save addition. The block drawing on the lower right of Figure B.14.1 (see below) shows the organization, with two levels of carry save adders connected by a single normal adder. Calculate the delays to add four 16-bit numbers using full carry-lookahead adders versus carry save with a carry-lookahead adder forming the final sum. (The time unit T in Exercise B.28 is the same)

Short Answer

Expert verified

The total required time is 5T.

Step by step solution

01

Define the concept.

This total time is required for every operand by not considering the bit.

5T time is taken from the path of consisting the inputs of “S1”, “S2”, “S3”.

For generating all of the signals of “p” and “g”, only a single cycle is taken.

For generating the “C3” to “C0” additional two cycles are required.

And for generating the “S3” to “S0” additional two cycles are required.

The “T” is referred to as the time unit.

02

Determine the calculation.

The adder:

In the Ripple carry adder one bit requires 2T time.

In this Carry Look Ahead Adder,

Action

Required time

To generate Piand Gi.

1T

To carry Ci

2T

To generate Sums Si.

2T

Hence,

Required time

Signals of adder

T=0

“A3”…”A0” ,“B3”...”B0”, C0

T=1

“G3”…”G0”

T=2

“S0”

T=3

“C1”,”C2”, “C3”, “C4”

T=5

“S1” ,”S2”,”S3”

Hence total required time is 5T.

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Most popular questions from this chapter

One logic function that is used for a variety of purposes(including within adders and to compute parity) is exclusive OR. The output of a two-input exclusive OR function is true only if exactly one of the inputs is true. Show the truth table for a two-input exclusive OR function and implement this function using AND gates, OR gates, and inverters

Question: Compilers can have a profound impact on the performance of an application. Assume that for a program., compiler A results in a dynamic instruction count of 1.0E9 and has an execution time of 1.1 s, while compiler B results in a dynamic instruction count of 1.2E9 and an execution time of 1.5 s.

  1. Find the average CPI for each program given that the processor has a clock cycle time of 1 ns.

  2. Assume the compiled programs run on two different processors. If the execution times on the two processors are the same, how much faster is the clock of the processor running compiler A’s code versus the clock of the processor running compiler B’s code?

  3. A new compiler is developed that uses only 6.0E8 instructions and has an average CPI of 1.1. What is the speedup of using this new compiler versus using compiler A or B on the original processor?

Assume a 15 cm diameter wafer has a cost of 12, contains 84 dies, and has 0.020 defects/cm2 . Assume a 20 cm diameter wafer has a cost of 15, contains 100 dies, and has 0.031 defects/cm2 .

1.10.1 Find the yield for both wafers.

1.10.2 Find the cost per die for both wafers.

1.10.3 If the number of dies per wafer is increased by 10% and the defects per area unit increases by 15%, find the die area and yield.

1.10.4 Assume a fabrication process improves the yield from 0.92 to 0.95. Find the defects per area unit for each version of the technology given a die area of 200 mm2

The Pentium 4 Prescott processor, released in 2004, had a clock rate of 3.6 GHz and voltage of 1.25 V. Assume that, on average, it consumed 10 W of static power and 90 W of dynamic power. The Core i5 Ivy Bridge, released in 2012, had a clock rate of 3.4 GHz and voltage of 0.9 V. Assume that, on average, it consumed 30 W of static power and 40 W of dynamic power.

1.8.1 For each processor find the average capacitive loads.

1.8.2 Find the percentage of the total dissipated power comprised by static power and the ratio of static power to dynamic power for each technology.

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B.20 [10] <§§B.3, B.4> Write down a Verilog module implementation of a 2-to-4 decoder (and/or encoder).

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