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B.30 [15] <§B.6> This exercise is similar to Exercises B.28 and B.29, but this time calculate the relative speeds of a 64-bit adder using ripple carry only, ripple carry of 4-bit groups that use carry lookahead, ripple carry of 16-bit groups that use carry lookahead, and the carry-lookahead scheme from Exercise B.27.

Short Answer

Expert verified

The relative speed is 128T.

Step by step solution

01

Define the concept.

The 64- bit adderhas the feature of carry propagating and carry generating.

For the carry propagating, the carry propagator (P) is used for propagating to the following state of this.

For carry generating, the carry generator (G) is used for generating the result query by not considering the carry of the input.

The computed sum of every 16-bit adder is represented by “S”.

The ripple carry adder is referred to as the digital circuit that can able to produce the arithmetical sum of the specified numbers. This also can construct by cascading the full adders. There is also a carry output from every full adder that is cascaded to the “carry input” of the following full adder in the sequence.

The “T” is referred to as the time unit.

In the Ripple carry adder one bit requires 2T time.

02

Determine the calculation.

In the Ripple carry adder one bit requires 2T time.

Hence,forthe64-bitripplecarryadder,thedelay=(64×2T)=128T

The new equation for the carry-look ahead logic (64- bit adder) that is implemented by the 16-bit adders, those are acted as the building block:

C1=G0+(P0×c0)C2=G1+(P1×G0)+(P1×P0×c0)C3=G2+(P2×G1)+(P2×P1×G0)+(P2×P1×P0×c0)

The diagram of the 64-bit adder by using the ripple-carry:

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Most popular questions from this chapter

Describe the steps that transform a program written in a high-level language such as C into a representation that is directly executed by a computer processor.

B.31 [10] <§B.6> Instead of thinking of an adder as a device that adds: two numbers and then links the carries together, we can think of the adder as a hardware device that can add three inputs together (ai, bi, ci) and produce two outputs (s, ci + 1). When adding two numbers together, there is little we can do with this observation. When we are adding more than two operands, it is possible to reduce the cost of the carry. The idea is to form two independent sums, called S (sum bits) and C (carry bits). At the end of the process, we need to add C and S together using a normal adder. This technique of delaying carry propagation until the end of a sum of numbers is called carry save addition. The block drawing on the lower right of Figure B.14.1 (see below) shows the organization, with two levels of carry save adders connected by a single normal adder. Calculate the delays to add four 16-bit numbers using full carry-lookahead adders versus carry save with a carry-lookahead adder forming the final sum. (The time unit T in Exercise B.28 is the same)

A.3 Is it ever safe for a user program to use registers \(k0 or \)k1?

Question: B.26 [5] <§B.6> Rewrite the equations on page B-44 for a carry-lookahead logic for a 16-bit adder using a new notation. First, use the names for the CarryIn signals of the individual bits of the adder. That is, use c4, c8, c12, … instead of C1, C2, C7, …. In addition, let Pi,j; mean a propagate signal for bits i to j, and Gi,j; mean a generate signal for bits i to j. For example, the equation

C2 = G1+( P1.G0)+( P1.P0. c0) can be rewritten as

c8= G 7,4 + (P7,4 .G7,0)+( P7,4 .P3,0.c0)

This more general notation is useful in creating wider adders.

The results of the SPEC CPU2006 bzip2 benchmark running on an AMD Barcelona has an instruction count of 2.389E12, an execution time of 750 s, and a reference time of 9650 s.

1.11.1 [5] <§§1.6, 1.9> Find the CPI if the clock cycle time is 0.333 ns.

1.11.2 [5] <§1.9> Find the SPECratio.

1.11.3 [5] <§§1.6, 1.9> Find the increase in CPU time if the number of instructions of the benchmark is increased by 10% without affecting the CPI.

1.11.4 [5] <§§1.6, 1.9> Find the increase in CPU time if the number of instructions of the benchmark is increased by 10% and the CPI is increased by 5%.

1.11.5 [5] <§§1.6, 1.9> Find the change in the SPECratio for this change.

1.11.6 [10] <§1.6> Suppose that we are developing a new version of the AMD Barcelona processor with a 4 GHz clock rate. We have added some additional instructions to the instruction set in such a way that the number of instructions has been reduced by 15%. Th e execution time is reduced to 700 s and the new SPECratio is 13.7. Find the new CPI.

1.11.7 [10] <§1.6> Th is CPI value is larger than obtained in 1.11.1 as the clock rate was increased from 3 GHz to 4 GHz. Determine whether the increase in the CPI is similar to that of the clock rate. If they are dissimilar, why?

1.11.8 [5] <§1.6> By how much has the CPU time been reduced?

58 Chapter 1 Computer Abstractions and Technology

1.11.9 [10] <§1.6> For a second benchmark, libquantum, assume an execution time of 960 ns, CPI of 1.61, and clock rate of 3 GHz. If the execution time is reduced by an additional 10% without aff ecting to the CPI and with a clock rate of 4 GHz, determine the number of instructions.

1.11.10 [10] <§1.6> Determine the clock rate required to give a further 10% reduction in CPU time while maintaining the number of instructions and with the CPI unchanged.

1.11.11 [10] <§1.6> Determine the clock rate if the CPI is reduced by 15% and the CPU time by 20% while the number of instructions is unchanged.

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