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B.30 [15] <§B.6> This exercise is similar to Exercises B.28 and B.29, but this time calculate the relative speeds of a 64-bit adder using ripple carry only, ripple carry of 4-bit groups that use carry lookahead, ripple carry of 16-bit groups that use carry lookahead, and the carry-lookahead scheme from Exercise B.27.

Short Answer

Expert verified

The relative speed is 32T.

Step by step solution

01

Define the concept.

The 16- bit adderhas the feature of carry propagating and carry generating.

For the carry propagating, the carry propagator (P) is used for propagating to the following state of this.

For carry generating, the carry generator (G) is used for generating the result query by not considering the carry of the input.

The computed sum of every 16-bit adder is represented by “S”.

The ripple carry adder is referred to as the digital circuit that can able to produce the arithmetical sum of the specified numbers. This also can construct by cascading the full adders. There is also a carry output from every full adder that is cascaded to the “carry input” of the following full adder in the sequence.

The “T” is referred to as the time unit.

In the Ripple carry adder one bit requires 2T time.

02

Determine the calculation.

In the Ripple carry adder one bit requires 2T time.

Hence, for the 16 - bit ripple carry adder, the delay =16×2T=32T

The diagram of the 16-bit adder by using the ripple-carry:

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Most popular questions from this chapter

Perhaps the most likely case of adding many numbers at once in a computer would be when trying to multiply more quickly by using any adders to add many numbers in a single clock cycle. Compared to the multiply algorithm in Chapter 3, a carry save scheme with many adders could multiply more than 10 times faster. This exercise estimates the cost and speed of a combinational multiplier to multiply two positive 16-bit numbers. Assume that you have 16 intermediate terms M15, M14, …, M0, called partial products, that contain the multiplicand ANDed with multiplier bits m15, m14, …, m0. The idea is to use carry save adders to reduce the noperands into 2n/3 in parallel groups of three, and do this repeatedly until you get two large numbers to add together with a traditional adder.

First, show the block organization of the 16-bit carry save adders to add these 16 terms, as shown on the right in Figure B.14.1. Then calculate the delays to add these 16 numbers. Compare this time to the iterative multiplication scheme in Chapter 3 but only assume 16 iterations using a 16-bit adder that has full carry lookahead whose speed was calculated in Exercise B.29.

B.16 [30] <§§B.2, B.3> Give an algorithm for constructing the sum-of- products representation for an arbitrary logic equation consisting of AND, OR, and NOT. The algorithm should be recursive and should not construct the truth table in the process.

Question:B.21 [10] <§§B.3, B.4> Given the following logic diagram for an accumulator, write down the Verilog module implementation of it. Assume a positive edgetriggered register and asynchronous Rst.

Question: B.26 [5] <§B.6> Rewrite the equations on page B-44 for a carry-lookahead logic for a 16-bit adder using a new notation. First, use the names for the CarryIn signals of the individual bits of the adder. That is, use c4, c8, c12, … instead of C1, C2, C7, …. In addition, let Pi,j; mean a propagate signal for bits i to j, and Gi,j; mean a generate signal for bits i to j. For example, the equation

C2 = G1+( P1.G0)+( P1.P0. c0) can be rewritten as

c8= G 7,4 + (P7,4 .G7,0)+( P7,4 .P3,0.c0)

This more general notation is useful in creating wider adders.

Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5.P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2.

a. Which processor has the highest performance expressed in instructions per second?

b. f the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions.

c. We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction?

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