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QuestionB.28 [10] <§B.6> Now calculate the relative performance of adders. Assume that hardware corresponding to any equation containing only OR or AND terms, such as the equations for pi and gi on page B-40, takes one time unit T. Equations that consist of the OR of several AND terms, such as the equations for c1, c2, c3, and c4 on page B-40, would thus take two time units, 2T. The reason is it would take T to produce the AND terms and then an additional T to produce the result of the OR. Calculate the numbers and performance ratio for 4-bit adders for both ripple carry and carry lookahead. If the terms in equations are further defined by other equations, then add the appropriate delays for those intermediate equations, and continue recursively until the actual input bits of the adder are used in an equation. Include a drawing of each adder labeled with the calculated delays and the path of the worst-case delay highlighted.

Short Answer

Expert verified

The relative performance of this adder:

Sum

Delay

Carry

Delay

S3

14

C4

19

Step by step solution

01

Define the concept.

The 4- bit adderhas the feature of carry propagating and carry generating.

For the carry propagating, the carry propagator (P) is used for propagating to the following state of this.

For carry generating, the carry generator (G) is used for generating the result query by not considering the carry of the input.

The computed sum of every 4-bit adder is represented by “S”.

T time is taken for producing the AND terms.

2T time is taken for each bit in the previous adder.

Hence the total required time is 8T, where “T” denotes the unit of time.

The relative performance of this adder:

Sum

Sn - 1[n represents the number of bit in adder]

Delay

4n - 2[n represents the number of bit in adder]

Carry

Cn[n represents the number of bit in adder]

Delay

4n + 3[n represents the number of bit in adder]

02

Determine the calculation.

Relative performance of this adder:

Sum

Delay

Carry

Delay

Sn - 1=S4 - 1=S3

4n - 2 =(4×4)-2=16 - 2 = 14

Cn=C4

4n + 3 =4×4+3 = 16 + 3 = 19

In the below mentioned figure-

  • A0 and B0 are the two inputs for the first 1 bit adder.
  • A1 and B1 are the two inputs for the second 1 bit adder.
  • A2 and B2 are the two inputs for the third 1-bit adder.
  • A3 and B3 are the two inputs for the fourth 1-bit adder.
  • C0 is the “carry” for the first 1-bit adder.
  • C1 is the “carry” for the second1-bit adder.
  • C2 is the “carry” for the third 1-bit adder.
  • C3 is the “carry” for the fourth 1-bit adder.
  • The “super” propagates are P3, P2, P1, and P0.
  • The “super” generator are G3, G2,G1, and G0.

The diagram of 4-bit adders with carry look ahead:

In the below mentioned figure-

  • C0 is the “carry” for the first 1-bit adder.
  • C1 is the “carry” for the second 1-bit adder.
  • C2 is the “carry” for the third 1-bit adder.
  • C3 is the “carry” for the fourth 1-bit adder.
  • A0 and B0 are the two inputs for the first 1-bit adder.
  • A1 and B1 are the two inputs for the second 1-bit adder.
  • A2 and B2 are the two inputs for the third 1-bit adder.
  • A3 and B3 are the two inputs for the fourth 1-bit adder.
  • The “super” propagates are P3, P2, P1, and P0.
  • The “super” generator are G3, G2,G1, and G0.

The diagram of 4-bit adders with ripple carry:

T time is taken for producing the AND terms.

2T time is taken for the each bit in the previous adder.

Hence the total required time is 8T, where “T” denotes the unit of time.

And the total required time for the adder by using “And” terms (4 x 1T) ==4T.

Ratio is (4 x 2T) : (4 x 1T) = 8T : 4T = 2: 1

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Most popular questions from this chapter

Assume a program requires the execution of50×106FP instructions, 110×106INT instructions,80×106L/S instructions, and16×106branch instructions. The CPI for each type of instruction is 1, 1, 4, and 2, respectively. Assume that the processor has a 2 GHz clock rate:

1.14.1 By how much must we improve the CPI of FP instructions if we want the program to run two times faster?

1.14.2 By how much must we improve the CPI of L/S instructions if we want the program to run two times faster?

1.14.3 By how much is the execution time of the program improved if the CPI of INT and FP instructions is reduced byand the CPI of L/S and Branch is reduced by?

Assume that X consists of 3 bits, x2 x1 x0, and Y consists of 3 bits, y2 y1 y0. Write logic functions that are true if and only if

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2 Section 1.10 cites as a pitfall the utilization of a subset of the performance equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4 GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3 GHz, an average CPI of 0.75, and requires the execution of 1.0E9 instructions.

1.12.1 [5] <§§1.6, 1.10> One usual fallacy is to consider the computer with the largest clock rate as having the largest performance. Check if this is true for P1 and P2.

1.12.2 [10] <§§1.6, 1.10> Another fallacy is to consider that the processor executing the largest number of instructions will need a larger CPU time. Considering that processor P1 is executing a sequence of 1.0E9 instructions and that the CPI of processors P1 and P2 do not change, determine the number of instructions that P2 can execute in the same time that P1 needs to execute 1.0E9 instructions.

1.12.3 [10] <§§1.6, 1.10> A common fallacy is to use MIPS (millions of

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