Question

B.22 [20] <§§B3, B.4, B.5> Section 3.3 presents basic operation and possible implementations of multipliers. A basic unit of such implementations is a shift - and-add unit. Show a Verilog implementation for this unit. Show how can you use this unit to build a 32-bit multiplier.

Short answer

The Verilog implementation for the specified unit:

$\begin{array}{l}\text{Module\_multiplier}\left({\text{s,clock,clear,B}}_{\text{in}}{\text{,Q}}_{\text{in}}\text{,W,Y,Z,B}\right)\\ \text{Inputs,clock,clearInput}\left[\text{4:0}\right]{\text{Q}}_{\text{in}}{\text{,B}}_{\text{in}}\text{;}\\ \text{Output}\left[\text{4:0}\right]\text{Y,Z;Output}\left[\text{2:0}\right]\text{B;}\\ \text{SystemregistersregC;}\\ \text{reg}\left[\text{4:0}\right]\text{Y,Z,B;}\\ \text{reg}\left[\text{2:0}\right]\text{B;}\\ \text{reg}\left[\text{2:0}\right]{\text{state}}_{\text{P}}{\text{,state}}_{\text{N}}\text{;}\\ \text{//combinationalcircuitwirez;}\\ \text{assignz=|B;}\begin{array}{l}\text{//stateregisterprocessforcontroller}\\ \text{Alwaysbegin}\\ \begin{array}{l}\\ {\text{ifstate}}_{\text{P}}\text{<=T0;}\end{array}\\ {\text{elsestate}}_{\text{P}}{\text{<=state}}_{\text{N}}\text{;}\\ \text{end}\end{array}\end{array}$

Step-by-step solution

Define the concept.

This basically represents the Verilog implementation. This unit is also a 32-bit multiplier.

In the Verilog, if operands are 32-bits then it returns a 64-bit output. Hence the 64 bit Verilog multiplier will be necessary for this purpose.

In the Verilog, if operands are 16-bits then it returns a 32-bit output. Hence the 32 bit Verilog multiplier will be necessary for this purpose. So, this Verilog multiplier is suitable for this.

Determine the calculation.

The process of using this unit for building a 32-bit multiplier:

//state transition process for controller

Always begin

Case ()

T0: if = T₁; else = T₀

T₁: = T₂;

T₂: = T₃;

T₃:if (z) = T0; else = T₂

Endcase

End