Question

Question:B.21 [10] <§§B.3, B.4> Given the following logic diagram for an accumulator, write down the Verilog module implementation of it. Assume a positive edgetriggered register and asynchronous Rst.

Short answer

Answer

The required Verilog module implementation:

module_verilog_accumulator(Q_In, L0, Clock, RESET, L1, Q_out);

input[15:0] L0, Q_In;

inputClock, RESET, L1;

Qoutput[15:0] Q_out t;

reg[15:0] Q_out;

always@(posedge RESET or posedge Clock) begin

if(RESET) Q_out <=0;

elseif (L1)

Q_out<=L0;

else

Q_out<= Q_out + Q_In;

end

End_module_verilog_accumulator

Step-by-step solution

Define the concept of the implementation

It is assumed in the above implementation that there is also a register of positive edge-triggered and Reset of asynchronous are present.

The above implementation is corresponding to the mentioned logic diagram.

Two loads are used in the above implementation- “LO” and “L1”.

Reset is acted like “Rst” and clock is also acted like “clk”. Q_in and Q_out are acted like “In” and “out” respectively.

Determine the implementation with comment. 

module_verilog_accumulator(Q_In, L0, Clock, RESET, L1, Q_out);

input[15:0] L0, Q_In;

inputClock, RESET, L1;

Qoutput[15:0] Q_out t;

reg[15:0] Q_out;

// initialized the state for the required accumulator

always@(posedge RESET or posedge Clock) begin

// checking for the condition for RESET with “if”

if(RESET) Q_out <=0;

// checking for the condition for L1 with “if”

elseif (L1)

Qout<=L0;

// When the condition of “if” statement becomes false

else

Q_out<= Q_out + Q_In;

end

// end of the required module

End_module_verilog_accumulator