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Instead of using four state bits to implement the finite-state machine in Figure D.3.1, use nine state bits, each of which is a 1 only if the finite-state machine is in that particular state (e.g., S1 is 1 in state 1. S2 is 1 in state 2, etc.). Redraw the PLA (Figure D.3.9).

Short Answer

Expert verified

The finite-state machine consists of finite states and transactions from one state to another state. Each state in finite state machine has a different name. In Figure D.3.1 of the textbook, each state in the finite-state machine is labelled using 4 state bits.

As there are total 10 states in the finite-state machine, 4 bits are sufficient to write the name of the state in binary. The four bits are represented as (S3, S2, S1, S0). The value 1001 means machine is in state 9 because the decimal equivalent of 1001 is 9.

Step by step solution

01

Define finite-state machine

The finite-state machine consists of finite states and transactions from one state to another state. Each state in finite state machine has a different name. In Figure D.3.1 of the textbook, each state in the finite-state machine is labelled using 4 state bits.

As there are total 10 states in the finite-state machine, 4 bits are sufficient to write the name of the state in binary. The four bits are represented as (S3, S2, S1, S0). The value 1001 means machine is in state 9 because the decimal equivalent of 1001 is 9.

02

Use 9 state bits to represent the states of the finite-state machine

The finite-state machine has 10 states (0-9). The particular bit of the 9-bit state is one if and only if that machine is in that state. Every state will be written in the following format:

(S9 S8 S7 S6 S5 S4 S3 S2 S1 S0)

For example, if the machine is in state 1, the S1 bit of 9 state bits is set to 1, rest will be 0. If the machine is in state 5, the S5 bit of the 9 state bits is set to 1, rest will be zero.

03

Define PLA

PLA is short for Programmable Logic Array. These are the logic devices. The combinational circuits are implemented using the PLAs. PLA consist of a set of AND gates followed by the OR gates. These provide control over data path and can also be used as counter or decoders.

04

Draw PLA using 9 state bits

The PLA will consist 9 state bits from S0 to S9. If the machine is in particular state, the corresponding operation for that particular state are highlighted in the PLA using black dot. For example, If the state is S0, the operations PCWrite, MemRead, ALUSrc80 are selected. Similarly, for the rest of the states, the corresponding operations are performed. The PLA for 9 state bit is shown below:

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Most popular questions from this chapter

B.30 [15] <§B.6> This exercise is similar to Exercises B.28 and B.29, but this time calculate the relative speeds of a 64-bit adder using ripple carry only, ripple carry of 4-bit groups that use carry lookahead, ripple carry of 16-bit groups that use carry lookahead, and the carry-lookahead scheme from Exercise B.27.

Perhaps the most likely case of adding many numbers at once in a computer would be when trying to multiply more quickly by using any adders to add many numbers in a single clock cycle. Compared to the multiply algorithm in Chapter 3, a carry save scheme with many adders could multiply more than 10 times faster. This exercise estimates the cost and speed of a combinational multiplier to multiply two positive 16-bit numbers. Assume that you have 16 intermediate terms M15, M14, …, M0, called partial products, that contain the multiplicand ANDed with multiplier bits m15, m14, …, m0. The idea is to use carry save adders to reduce the noperands into 2n/3 in parallel groups of three, and do this repeatedly until you get two large numbers to add together with a traditional adder.

First, show the block organization of the 16-bit carry save adders to add these 16 terms, as shown on the right in Figure B.14.1. Then calculate the delays to add these 16 numbers. Compare this time to the iterative multiplication scheme in Chapter 3 but only assume 16 iterations using a 16-bit adder that has full carry lookahead whose speed was calculated in Exercise B.29.

A simple check for overflow during addition is to see if the CarryIn to the most significant bit is not the same as the CarryOut of the most significant bit. Prove that this check is the same as in Figure 3.2.

B.20 [10] <§§B.3, B.4> Write down a Verilog module implementation of a 2-to-4 decoder (and/or encoder).

Assume a color display using 8 bits for each of the primary colors (red, green, blue) per pixel and a frame size of 1280 × 1024. a. What is the minimum size in bytes of the frame buffer to store a frame? b. How long would it take, at a minimum, for the frame to be sent over a 100 Mbit/s network?

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