Chapter 1: Q19E (page 2)
B .19 [5] <§B.4>The Verilog code on page B-53 is for a D flip-flop. Show the Verilog code for a D latch.
Short Answer
The Verilog code for a D latch:
Chapter 1: Q19E (page 2)
B .19 [5] <§B.4>The Verilog code on page B-53 is for a D flip-flop. Show the Verilog code for a D latch.
The Verilog code for a D latch:
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Get started for freeB.20 [10] <§§B.3, B.4> Write down a Verilog module implementation of a 2-to-4 decoder (and/or encoder).
A.9 [25] Write and test a MIPS assembly language program to compute and print the first 100 prime numbers. A number n is prime if no numbers except 1 and n divide it evenly. You should implement two routines: ■ test_prime (n) Return 1 if n is prime and 0 if n is not prime. ■ main () Iterate over the integers, testing if each is prime. Print the first 100 numbers that are prime. Test your programs by running them on SPIM.
Question: B.23 [20] <§§B3, B.4, B.5> Repeat Exercise B.22, but for an unsigned divider rather than a multiplier.
Assume a color display using 8 bits for each of the primary colors (red, green, blue) per pixel and a frame size of 1280 × 1024. a. What is the minimum size in bytes of the frame buffer to store a frame? b. How long would it take, at a minimum, for the frame to be sent over a 100 Mbit/s network?
Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5.P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2.
a. Which processor has the highest performance expressed in instructions per second?
b. f the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions.
c. We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction?
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