VHDL

Introduction to Language VHDL

 ENTITY entity_name IS 
PORT ( port_name : mode port_type ); 
END entity_name; 

ARCHITECTURE architecture_name OF entity_name IS 
BEGIN 
END architecture_name; 

CONFIGURATION config_name OF entity_name IS 
FOR architecture_name 
END FOR; 
END config_name; 

Foundation of VHDL code

 ENTITY flip_flop IS 
PORT ( D, CLK : IN STD_LOGIC; Q : OUT STD_LOGIC ); 
END flip_flop;

ARCHITECTURE behavior OF flip_flop IS 
BEGIN 
process(D, CLK) 
  if rising_edge(CLK) then Q <= D; 
  end if; 
END process; 
END behavior; 

Types of Variables and Data in VHDL

• bit: Represents a binary value (0 or 1).
• boolean: Represents a logical value (true or false).
• integer: Represents a signed whole number.
• real: Represents a floating-point number.

Not equal VHDL: Understanding Inequalities

 IF signal1 /= signal2 THEN 
-- execute if not equal 
END IF; 

Working with Control Structures in VHDL

Dive Deep into VHDL for loop

 FOR i IN range LOOP 
-- Statements 
END LOOP; 

 FOR i IN 0 TO 10 LOOP -- Ascending 
FOR i IN 10 DOWNTO 0 LOOP -- Descending 

Utilising for loop for repetitive tasks in VHDL

 FOR i IN 0 TO 9 LOOP 
array(i) <= '0'; 
END LOOP; 

Importance of VHDL if statement

 IF condition THEN 
-- Statements if condition is true 
ELSIF another_condition THEN 
-- Statements if another_condition is true 
ELSE 
-- Statements if no conditions are true 
END IF; 

Creating conditions with VHDL if statement

 IF signal1 > signal2 THEN 
-- execute if signal1 is greater than signal2 
END IF; 

The VHDL case statement Explained

 CASE expression IS 
WHEN value1 => 
-- Statements for value1 
WHEN value2 => 
-- Statements for value2 
... 
WHEN OTHERS => 
-- Statements for values not included above 
END CASE; 

Implementing decision-making using VHDL case statement

 CASE state IS 
WHEN 'stop' => 
-- execute stop state logic 
WHEN 'go' => 
-- execute go state logic 
WHEN 'wait' => 
-- execute wait state logic 
END CASE; 

VHDL Examples and Applications

How 2 bit comparator VHDL with select code works

 
ENTITY Comparator IS 
   PORT ( A, B : IN integer range 0 to 3; 
          L, G, E : OUT std_logic 
        ); 
END Comparator; 

ARCHITECTURE Behavior OF Comparator IS 
BEGIN 
   WITH A SELECT 
      L <= '1' when 0, 
           '0' when others; 
      G <= '0' when 0, 
           '1' when others; 
      E <= '1' when B, 
           '0' when others; 
END Behavior; 

Real-life example of 2 bit comparator VHDL application

Working with VHDL code: A step-by-step guide and examples

 ENTITY entity_name IS 
PORT ( port_name : mode port_type ); 
END entity_name; 

 ENTITY AND_Gate IS 
PORT ( A, B : IN STD_LOGIC; 
       Z : OUT STD_LOGIC); 
END AND_Gate; 

 ARCHITECTURE architecture_name OF entity_name IS 
BEGIN 
-- logic 
END architecture_name; 

 ARCHITECTURE Dataflow OF AND_Gate IS 
BEGIN 
Z <= A AND B; 
END Dataflow; 

Using VHDL in computer organisation and architecture