Verilog

Understanding Verilog and its Importance in Computer Architecture

• It aids in the design of complex digital systems from conceptualization to implementation.
• Verilog assists in specifying the circuit's behaviour in the testing phase.
• It facilitates simplified modelling of a digital system at various levels.

Key Concepts of Verilog for Beginners

 
module Test(input a, input b, output q);
   assign q = a & b;
endmodule

• Data types: There are four primary data types in Verilog: nets, registers, integers, and reals.
• Operators: Verilog provides a rich set of operators. These can be categorised into arithmetic, relational, logical, and bit-wise operators.
• Control Statements: Similar to other programming languages, Verilog also has control statements such as if, case, for loop, while loop and repeat loop.

module counter (clk, reset, q);
   input  clk, reset;
   output [3:0] q;

   reg [3:0] q;

   always @(posedge clk or posedge reset)
     if (reset) 
       q <= 4'b0;
     else 
       q <= q + 1'b1;
endmodule

Developments and Advancements in Verilog

Evolution from Verilog to System Verilog

• High-level abstract description for system-level design.
• Enhanced test structure for system validation.
• Packed with hardware verification language (HVL) capabilities.

integer i;
i = 4;

int i;
i = 4;

Comparative Analysis: Verilog VS VHDL

Role of Verilog Operators in these Developments

assign c = a + b;

Exploring Verilog in Detail

Working with Verilog Case Statement

case (exp)
  exp1: statement1;
  exp2: statement2;
  default: statementd;
endcase

• casex allows matching with don’t care conditions (x or X) in the case expression.
• casez allows matching with high impedance conditions (z or Z) in the case expression.

casex (bus)
  3'b1x0: $display ("Bus is either 100 or 110");
  3'b0x0: $display ("Bus is either 000 or 010");
  default: $display ("No match found");
endcase

Application of Verilog For Loop in Programming

for (initialise; condition; increment)
  begin
  statement;
  end

Practical Verilog Examples for Effective Learning

module case_example ();
 reg [3:0] binary_digit;
 initial begin
 case(binary_digit)
 4'b0000: $display("Binary value is 0000");
 4'b0001: $display("Binary value is 0001");
 default: $display("Binary value is none of the specified values");
 endcase 
 end 
endmodule

module Forloop_Example;
  integer num;
  initial begin
    for(num = 0; num < 5; num = num + 1)
    begin
       $display ("Value of num: %0d", num);
    end
  end
endmodule